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February 2014 • SMT Magazine 23 combined with the higher variation produced in this set of tests, indicated a considerable pro- cess difference somewhere in the experiment. The sources of variation were explored. First, the test setup and equipment were in- vestigated via a database search. The test runs always took place on after the first shift finished using the printer, over a course of two weeks. Investigation into the production print yields indicated no out-of-control situations on the assembly line during that time period; print yields for all production prints run on that line were within in their typical 98%+ range. The likelihood of the printer or print test method introducing the variation was unlikely. Next, the performance of the stencils cut ac- cording to the POR—1, 5 and 7 were compared. FINe-TuNING THe STeNCIL MaNuFaCTurING PrOCeSS continues Issues had already been identified with stencil 1's PCB side topography that produced atypical results, but stencils 5 and 7 did not produce re- sults comparable with each other (stencil 7 had the highest CV of the tests). These stencils were all manufactured using the Process of Record, with one exception: The usual production sten- cils are manufactured at a local facility, whereas the test stencils were produced at one of the supplier's other sites. To explore the possibility of differences in the two sites' manufacturing processes, the pro- duction stencil for this PCB was print tested us- ing the same 10-print test as the other runs. It yielded 100% (Figure 19) and transferred 83% (Figure 20) with 9.6% variation (Figure 21), cor- relating with historical data. FEATUrE Figure 18: Effect of extending wipe frequency on volume repeatability. Figure 20: Transfer efficiencies for theoretically identical stencils. Figure 19: Print yields for theoretically identical stencils. Figure 21: Volume repeatability for theoretically identical stencils.