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March 2014 • The PCB Design Magazine 45 c) determining a via-in-pad that will allow for PCB manufacturers to reliably drill and plate the inner pins so they may be contacted using non-component side layers of the PCB Most PCB manufacturers are able to apply solder mask down to 0.0635 mm (2.5 mils) and will guarantee that they can create a void in solder mask down to the same size. There- fore, to be certain every PCB will have solder mask applied between each pin while keeping the pins free from solder mask, it is recommended that at least 0.1905 mm of clearance is maintained in between each pin. This is equal to having two solder mask void widths (one for each pin) and one ap- plication width (gap between pins). For this package, the ball size is 0.268 mm +/- 0.06 mm with a pitch of 0.4 mm that leaves only 0.072 mm in be- tween the pads if we design for the maximum possible diameter. This will leave insufficient separation for solder masking to be reliably applied; there- fore it is not acceptable to design the pin diam- eter at 0.328 mm. Now faced with a tradeoff, the highest yield design option is to apply the necessary solder mask bridge between pins and sacrifice the solder mask void. This tradeoff is valid because the diameter of the pin will be included in the solder mask free area which will allow for adequate registration of the void, while giving the PCB manufacturer the needed solder mask width for guaranteed application. By specifying the pin diameter at 0.268 mm and the solder mask void diameter at 0.3315 mm, this leaves 0.0685 mm for sol- der mask, which provides crucial extra width since insufficient solder mask will lead to solder shorts under the package. Solder shorts under such packages are impossible to repair without removing and replacing the IC, an operation with lower success rates than the original as- sembly, due to the complication of applying a single device in a congested area on a poten- tially suspect footprint. With these diameters, the clearance from the solder mask to the pin is only half of the recommended clearance of 0.0635 mm; however, since the solder mask is not applied over the pin, that area is included in the void, thus the risk of having solder mask on the pin is reduced. Even if the pin does get partially covered, the risk is that the electrical connection could be re- duced by up to 12% of the available pin area. This compromise still leaves 88% guaranteed contact area between the CSP pin and the PCB pin, thus allowing even PCBs created on the low end of the tolerance band to still function with most likely unnoticeable defects. Another complication with such a de- vice is the need to use via-in- pads to access the inner pins (rows B–F and columns 2–5) followed up by back-filling the vias so that the pins may be plated on the surface until they are flat and even with the rest of the PCB copper. Typical vias require that the finished pad diameter is 0.127 mm wider than the finished plated hole diameter and the typical minimum via diameter without a surcharge is 0.127 mm–0.1524 mm. For the 0.268 mm pins requiring vias-in-pad, the solu- tion is to avoid using the minimum via while still allowing for manufacturing tolerances, thus a 0.15 mm via is recommended, leaving only 0.059 mm of pad diameter for registration and drill tolerance. Once the hole is drilled, the selection of the filling material should be con- sidered. There are two types of back-filling material in use: conductive and non-conductive. Besides the obvious difference, it should be noted that even the conductive fill material conductivity does not approach that of copper (electrically or thermally) and most have expansion coeffi- cients that are very different than the surround- ing via wall. During temperature variations of the PCB, non-conductive fill more frequently stretches and cracks the thin via walls compared to its counter-part, causing a higher percentage of intermittent or permanent failures. On the Even if the pin does get partially covered, the risk is that the electrical connection could be reduced by up to 12% of the available pin area. " " article PROPERLy DESIGNING PCB FOOTPRINTS continues