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46 The PCB Design Magazine • March 2014 other hand, non-conductive fill materials coef- ficient of expansion is typically closer to the vias plating and since the via plating will conduct the majority of the current and potential heat regardless of the type, the non-conductive fill is recommended for most applications. Finally, the package keepout should be specified such that at least 0.127 mm of free space surrounds each package in every direction. On such fine-pitch components, there are layout techniques that should be implement- ed to improve yield by reducing the chance of solder shorts or open circuits and that is to not place solid copper planes under the pins on the component side of the device. Adjacent pins that need to be connected to each other electrically should be connected using vertical and/or horizontal traces that match, or are less than the pin diameter in width in a grid type of an array. This is recommended so that in case the solder mask chips under the device during solder paste application (or for any reason), the risk of shorts or open circuits is greatly reduced because the solder will have fewer opportunities to excessively accumulate or spread away from the pin location during assembly. The next package under inspection is the DFN 2x2 mm or SC70 6 lead device, typically used to hold power transistors or other min- iature integrated circuits. Such devices are still relatively small, but they have slightly larger ge- ometries than the CSPs from above and allow the designer to follow standard PCB manufac- turing process capabilities. For example, on this device the solder mask voids and applications can be set to 0.0635 mm or greater, and the listed dimensions in Figure 2 are recommended for the pin, solder mask and paste mask sizes. Furthermore, such devices contain quite small silicon and usually need to spread the heat de- veloped away from the die in an effective man- ner in order to keep the operating temperature to an acceptable level. Vias-in-pads are neces- sary in order to utilize inner layers to spread the heat from the package into the PCB. The signifi- cant design challenge is to maintain 0.127 mm or more of etch surrounding each via for ease of plating and manufacturing. The spacing and diameter of such vias may vary from package- to-package based on available space and the number of vias will substantially improve the operating temperature of the device 1 . As can be seen in Figure 2, the lower center pin does not have 0.127 mm of etch on the top or bottom of the two vias; this is still accept- able since the vias have extra surface area on each side. When a through-hole is designed and 0.127 mm of pad ring cannot fit, creating an ob- Figure 2: DFn 2x2 mm 6 leAD (sC-70 6lD) single transistor package. article PROPERLy DESIGNING PCB FOOTPRINTS continues