Issue link: https://iconnect007.uberflip.com/i/291105
April 2014 • The PCB Magazine 17 LEAD-FREE REFLOW FOR HIGH-LAYER-COUNT PCBS continues Layer Assignment (Architecture) Blind microvias are a surface feature. In or- der to help reduce the number of layers of a tra- ditional multilayer with microvias, more work needs to be performed on the three surface lay- ers of each side of the board. This is illustrated in Figure 3. First priority is to reduce and eliminate through-vias. These block routing channels on the innerlayers. By eliminating 25% of the TH, two to three times as many traces can be routed on the innerlayers. One way to do this is to move the ground-plane (usually on layer 2) to the surface and use the microvias as via-in- pad (VIP) or near-via-in-pad (NVIP). This elimi- nates the most abundant vias on the boards— the ones to ground. In non-critical areas, this surface ground pour can be connected to other ground layers. The second most abundant vias are to power, so by moving this plane to layer 2, a blind via can connect SMT pads to this plane and not be very deep. Signals will start on layer 3, and depending on line-width, these skip-vias will not be very deep and will have a conven- tional aspect ratio and land size. If higher wiring density is required, then layer 2 and 3 should be signals. If fine lines are used (~3 mil), then skip vias will allow X-Y con- nections, otherwise, buried vias (type II) or bur- ied microvias (type III) are required to connect the two signal layers. Routing BGAs Using Channels Noting the importance of using the blind microvias to eliminate TH, a second impor- tant function, especially on large boards that have high I/O BGAs, is where the microvias are placed. Historically, the blind vias were placed around the perimeter of the BGA. This works well for BGAs with <400 pins, but for the new BGAs, like FPGAs, which contain 300 to more than 1700 pins, the blind vias are placed differ- Figure 3: Various layer assignments available when using Hdi and microvias. the goal is to remove as many tH as possible to free up routing space on the innerlayers.