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24 The PCB Magazine • April 2014 all about the drive to sub 35 micron lines and spaces. And the half-etch process is one way to achieve this goal. The basic concept of half-etch is to remove a set amount of copper from the surface in as uniform a fashion as possible. By etching the copper foil down to a lower thick- ness, the etch factor and resulting undercut is greatly reduced. Consequently, minimal copper is lost from the circuit trace. To insure this op- eration is successful, both chemistry and equip- ment configuration designs are critical. First and foremost, etching chemistry should etch down in the Z-axis as fast as possible. Second- ly the etching equipment must be designed to move the solution across the copper foils uni- formly. By reducing for example 1 ounce copper foil (35 microns) down to ½ ounce or ¼ ounce, one maintains the adhesion of the original foil. In addition, the fabricator is presented with a much thinner substrate foil that can be easily etched during the final etch process. There are several good reasons for this approach: • Minimize undercut and increase fine line yields • Ease of handling as opposed to working with ultra thin copper foils • Adhesion of the half-etched foil is usually greater than the adhesion of the ultra thin foil to the resin materials as well as the plated copper in the SAP (semi-additive process) With respect to the half-etch process, the etching chemistry should be designed to re- move the copper in a controlled fashion, im- parting minimal roughness to the remaining copper. This author has found that the desired etch rate on the copper foil (whether HTE or ED foil) for the half-etch process is 0.10–0.25 mi- crons per second (4–10 µin per second or 240– 600 µin per minute). One can achieve higher etch rates if desired. However, there needs to be a balance between chemical consumption, etch equipment compatibility and overall process control. Removing copper too fast could cause the heat to rise in the etching chamber. In ad- dition, it is beneficial to process the innerlayer foils through an acidic cleaner that will remove chromate and mild soils prior to actually etch- ing the copper. This helps to ensure a clean virgin copper surface that permits the etching chemistry to remove copper uniformly. Example of Telecom Redesign A major telecommunication company re- cently experimented with this concept. They took a recent 22-layer, TH optical-input board (0.127" thick) and redesigned it to a 14-layer HDI board of 0.063" thickness (1+12+1), with- out moving or changing any part locations. Fig- ure 9 shows the old 22-layer stackup compared to the new 14-layer HDI stackup. The boards were 8.50" by 14.34" with 702 parts (mostly BGAs and actives), having 8,759 pins on the PRI side and 2,036 parts (mostly passives) hav- ing 4,206 pins on the SEC side. There were ori- gnally 12,610 drilled TH in the original version, but only 3,887 in the HDI version; the rest were laser-drilled microvias. Conclusion One of the more difficult type of multilayer to get to accept a lead-free assembly process is the thick, high-layer count PCB with through- hole parts and multiple PWR/GND planes. HDI techniques can help in the reduction of thickness and number of layers for these types of boards, resulting in thinner multilayers, but also reducing the costs by 50% and im- proving the high-frequency performance and reliability. Further, the fabricator can enhance the overall relaibility and manufacturability of LEAD-FREE REFLOW FOR HIGH-LAYER-COUNT PCBS continues Figure 10: excessive cte leading to plated copper lifting from filled via.