Issue link: https://iconnect007.uberflip.com/i/293694
16 The PCB Design Magazine • April 2014 square of the trace height above the plane di- vided by the square of the separation distance. This illustrates an important point: that placing the trace closer to the reference plane will re- duce crosstalk even if the trace spacing remains the same. This provides an effective way to re- duce crosstalk without using up valuable real estate on the board which would be the case if the trace separation were increased. Now that we have established the fact that the return current follows the path of least in- ductance, and that it has a defined distribution in the reference plane, we need to now look at how the return current propagates in the planes. Figure 2 shows the ICD Stackup Planner [4] cre- ating an 8-layer stackup for an iMX53 processor and DDR2 memory combination. In this case, layers 1 & 3 and layers 6 & 8 are used for the layer pairs and all routing encircles the ground planes on layers 2 & 7. Since the ground is referenced in all cases, ground stitching vias can be placed near layer transitions (vias) to allow the return current to change planes where required. This limits the loop area, and hence the radiation. Or, would a buildup microstrip layer be bet- ter if you are risk-aversive? In Figure 3, I have added another buildup layer to the stackup (top and bottom). Copper plating on outer layers at- tributes considerable variations in trace width and thickness, hence impedance variations. You should avoid routing controlled impedance signals on these layers, but they can be used for feature MyTHBuSTING: THERE ARE NO ONE-WAy TRIPS! continues Figure 2: An 8-layer stackup using isola 370hr, 5ghz material. Figure 3: 10-layer buildup alternative stackup (only top shown).