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32 SMT Magazine • May 2014 participants in these trials were an HDI PCB manufacturer (AT&S) and its material suppliers. Introduction Continual miniaturization and RoHS re- quirements have significantly aggravated the endeavor to achieve customer ex- pectations in terms of reliable electronic devices. Drop shock performance has especially be- come an important factor in the past several years, due to the increasing number of por- table electronics, such as mo- bile devices, MP3 players and tablet computers. Many investigations have shown that the interaction of solder paste and surface finish, material selection and the ri- gidity of the whole electronic construct all have an impact on the final drop shock per- formance. Even an optimum combination of the before mentioned factors might not be enough to ensure a satis- fying quality of drop shock resistance, without factor- ing in critical design features and component selection. It is common to lower such risks with an under filling step between surface mount com- ponents and the printed circuit board. The efficiency of such an ad- ditional step strongly depends on the adhesion between solder mask and underfill material. The investigations for this article include a full factorial drop test DOE (design of experi- ments) and a new method to predict drop shock performance based on the knowledge of the surface energy of solder mask and underfill ma- terial. Test Equipment & method The drop test was performed based on an AT&S internal standard (mobile devices), which was evaluated and developed in conjunction with mobile device customers to meet their spe- cific requirements. A correlation between JEDEC JESD22-B111i and our mobile device standard might be difficult in terms of absolute number of drops, but it can be compared to determine basic trends (failure mode and time to failure results are similar). For the intent of this article, the material was the major focus, not the overall design. The PWB level drop tester was calibrated daily before starting any actual DOE mea- surements. The test vehicles were assembled with 12 dum- my components and flat rib- bon cables [1] soldered to the PTH terminals. To minimize the risk of solder joint failure of the signal cables during drop shock stress, the joints have been additionally fixed with a common available 3M tape. Furthermore the cables were fixed to the test equip- ment in such a way that the stress during test was reduced to a minimum (Table 1). Test vehicles The PCB build-up for the 30.7 mil thick DOE samples was an 8-layer multilayer with a common available halogen-free 150TG FR-4 ma- terial. The soldering was per- formed with a 4 mil thick elec- tro-polished stainless steel stencil, glued into polyester mesh and tensioned in an aluminum frame. The outer stencil dimensions were 736 x 736 x 40 mm. A commonly avail- able SAC type 3 solder was used for assembly. The underfilling material was based on a single- component epoxy system with fast curing, low CTE and Pb-free compatible behavior. In the ta- ble below, the three steps of sample production (multilayer, assembled multilayer & assembled multilayer after underfilling) is shown. The DOE layout was full factorial with four factors, each with two sub groups (see Table 3). Besides the main focus on solder mask type and underfill, the influence of pad design and sur- mECHaNICaL RELIaBILITy continues feATuRe Many investigations have shown that the interaction of solder paste and surface finish, material selection and the rigidity of the whole electronic construct all have an impact on the final drop shock performance. Even an optimum combination of the before mentioned factors might not be enough to ensure a satisfying quality of drop shock resistance, without factoring in critical design features and component selection. " "