Issue link: https://iconnect007.uberflip.com/i/344372
July 2014 • The PCB Design Magazine 19 a common database (no need to partition the design first). This has the added benefit of re- source flexibility—if there's no up-front parti- tioning pain, there's no problem adding team resources where necessary for short intervals to accelerate a project. Optimization of designs for signal and pow- er integrity is transitioning from isolated spe- cialists (leveraging the inter-discipline collabo- ration model) to every design engineer. This means that the engineers must also be able to access simulation tools directly from the sche- matic, and transfer rules developed through analysis directly into the constraint system. Most systems today allow definition of con- straints within the schematic, a significant ad- vancement from the days when spreadsheets were passed to the layout designer for inclusion. If you have multiple engineers working on the schematic, you also must allow concurrent con- straint entry. Taking it a step further, since the layout team also needs to see the constraints, they must be able to access and edit constraints along with the engineers. The real fun with true concurrent design comes at the layout stage. Without a parti- tioning hurdle, designers could jump into a design at any time. True concurrency means no boundaries, and no task limitations (i.e., it should work for placement, routing, plane defi- nition, manufacturing preparation, etc). A side benefit of this approach is mentoring—a junior designer could work alongside a senior design- er to learn best practices (in reality they could be on opposite sides of the planet). Design re- views and/or validation could happen concur- rently with design. Some teams segregate de- sign by functional boundaries (analog, SerDes, DDRx, RF); you could call this inter-discipline collaboration, but I've included it in this sec- tion since they all use the same tool for layout. And as you'd expect, true concurrency should allow all of these specialists to work in parallel, as shown in Figure 5. OPTIMIzINg COLLABORATION FOR PCB SySTEMS DESIgN continues feature Figure 5: Concurrent layout can shorten the completion time significantly.