Issue link: https://iconnect007.uberflip.com/i/396835
October 2014 • The PCB Design Magazine 19 SINk OR SWIM AT 28 GBPS continues feature are identified, the final step is to run the post- layout analysis on all 27 structures on the vali- dation platform and compare magnitude and phase of S-parameters, TDR and eye diagrams for 28 Gbps signals. Note, that before proceed- ing with the post-layout analysis and even be- fore the material model identification step, all stackup and trace width adjustments made by the PCB manufacturer must be discovered. If no information is available, the board has to be cross-sectioned to proceed further. PCBs are rarely manufactured as they appear in your fa- vorite layout tool, but a post-layout analysis tool usually takes geometry directly from the board design files. Changes in stackup, trace width and shape, and via back-drilling have to be verified and applied to the interconnect ge- ometry consistently before running any anal- ysis. Believe it or not, even the most accurate electromagnetic solver will produce garbage results without proper geometry description. Note that these manufacturing variations in- troduce additional uncertainties, and they usu- ally cause discrepancies at frequencies above 20–30 GHz and so far cannot be properly ac- counted for. The validation can be done in two ways: for just the PCB interconnect part with de-embed- ded connectors, or for complete link paths with the connectors and optionally adapters (exactly as measured in step 1). De-embedding is the ad- ditional step that can be problematic and error- prone. From the earlier validation experience [4] we have learned that the de-embedding of PCB structures with TRL procedure produces accept- able results only for highly reflective structures such as resonators or highly reflective vias. The highly reflective structures can be used to vali- date the software, but they are not typical for the actual interconnects with the minimized reflection. TRL de-embedding produces large errors in the reflection for the typical low-re- flective structures. It makes it difficult or even practically impossible to use TDR for the valida- Figure 4: GMS parameters computed from S-parameters measured for 2- and 8-inch microstrip line segments (red and blue lines) and modeled for 6-inch microstrip line segment (brown and green lines) with the same Fr408Hr model as for the stripline and wideband Debye model for solder mask with Dk=3.85, LT=0.02 @ 1 GHz and Modified Hammerstad conductor surface roughness model with Sr=0.4 um, rF=3.5.