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38 SMT Magazine • November 2014 new bare boards arrive sooner than reworked ones, thus eliminating the need for board-level ECO/ECNs. Timing of these changes needs to be such that the supply pipeline does not have any discontinuity. There are a variety of options available to the assembler or OEM for revising or fixing board errors. One of the options for fixing a lay- out, design or fabrication error, or to change the routing due to the use of another part configu- ration, is the respinning of a PCB. This involves the design or layout engineer revising the lay- out in the design software, redoing the output and re-sending the output files back to the PCB fabricator. It may take a couple of days to a cou- ple of weeks to get the pipeline filled up again with new PCBs using this option. In some cases a combination of both new- ly laid out, manufactured PCBs and modified boards that have been through the ECO/ECN process may be used. The ECO process may take place on the bare or populated boards. In order to keep the supply chain filled up, enough PCBs will need to be immediately modified while the process of changing the design, outputting new- ly revised Gerbers, manufacturing new boards, shipping and inspecting them, is completed. The start-to-finish time of getting newly manu- factured boards back to the assembly operation may be several weeks. This timeline may be ex- tended by several weeks if retesting of the new design is required. A variety of different types of physical modi- fications may be required as part of the ECO/ board modification stream on bare boards. The most common types of physical modification of PCBs include: conductor/trace/pad additions, conductor/trace cuts, selective solder mask re- moval, and physical board modifications such as the cutting of holes, the shaving of board outlines, or the creation of different physical geometries in order to get the board to properly fit/seat in a housing. There are some cases in which conductive traces must be added to the visible surfaces of a PCB. There are also board modifications re- quired in which test points or additional pads are added to the layout. This is very straight- forward when the trace or pad can be made or modified from an underlying ground layer and the solder mask can be selectively removed from the PCB (Figures 1 and 2). In other cases, one or more traces must be added in areas where there is not an underlying electrical connection to the first ground layer, or when there are many conductive runs which need to be added. Besides adding traces, in some cases errant signals are being picked up from traces in ad- dition to incorrect connections between two conductors on the board. In these scenarios, a conductor run or runs must be severed and properly insulated (Figure 3). In some cases, solder mask needs to be se- lectively removed in order to gain the proper figure 1: initial area of the board requiring both trace additions and circuit trace cuts. Figure 2: after modification where both a trace has been cut and another one added. feaTure bare boarD ecos, ecns anD Design moDiFications continues