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December 2014 • SMT Magazine 43 computing and telecommunications PCBAs we produce at Sanmina, for example, the cost of a single PCBA may be over $15,000. Therefore, it is imperative that the assembly is not damaged during rework. Furthermore, adequate spacing between components is also required to ensure that heat used for rework does not damage the solder joints of adjacent components, or the components themselves. While IPC standards do not provide strict requirements for component spacing, and cur- rent SMT assembly processes can accommodate tight spacings, experience has shown that at least 200 mils of space should be left around large ball-grid arrays to allow for rework. OEMs are placing decoupling capacitors as close as 40 mils in order to optimize noise performance. EMS companies are working with equipment manufacturers to develop processes and rework tooling that make reliable, repeatable rework possible, without inducing secondary reflow or additional rework of adjacent components. Although current solutions exist for keep-out space values well below 200 mils, additional process development and tooling enhance- ments are necessary to achieve tighter compo- nent spacing. challenge No. 3: chip Package Warpage To minimize cost, ICs are often mounted in plastic packages. However, plastic is less stable for example than ceramic. When plastic pack- ages are exposed to high temperatures during reflow, the package can warp: 2–10 mils or more, depending on the substrate, plastic material properties, package thickness and package size. A combination of package and PCB substrate dynamic warpage, along with PCB pad solder- ablity issues, variations in printed solder paste volume can result in solder defects between a device and the PCB. Two common defects are head-on-pillow (HOP), or non-wet open (NWO) type defects. While NWO defects create solder joints with no electrical continuity, HOP defects can be in- termittent and/or unreliable. Therefore, test- ing for HOP defects is a challenge and as such, time-consuming and resource-intensive screen- ing processes are needed in order to prevent products with these defects from getting into the field. The JEDEC specification for package warp- age, revised in 2005 and republished in 2009, al- lows for a maximum of 8 mils of co-planarity at FEATurE SUrFAce mOUNT TecHNOLOGY AdvANcemeNTS IN 2015 continues Figure 3: BgA pad cross-section, showing good wetting. Figure 4: BgA pad cross-section, showing a typical head-on-pillow (Hop) defect.