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46 The PCB Magazine • August 2015 LATENT SHoRT CIRCUIT FAILURE IN HIGH-REL PCBS continues are easier to detect compared to the latent short circuit caused by electromigration. C. Sources of Contamination Contamination of dielectric materials can occur in the PCB manufacturing process and in base material manufacturing. PCB manufactur- ers procure copper-clad laminate and prepreg sheets from base material suppliers. The PCB manufacturer is in control of cleanliness in pre- preg layers and on the surface of etched inner- layers. The base material supplier is in control of the cleanliness inside copper-clad laminate and also of the cleanliness of prepreg. PCB manufacturers report poor cleanliness levels in base materials and low yield as a re- sult. In addition, audits of PCB manufacturers show that there is variation in cleanliness of the manufacturing environment and in the clean- ing methods used on internal layers. D. PCB design IPC-2221 is the standard that is commonly used to specify insulation distance in a PCB as a function of voltage. Manufacturing tolerances are often overlooked when implementing de- sign rules. In one failed PCB assembly, a 4-mil (100 µm) laminate was used to accommodate a voltage of 100 V between copper planes. This was intended to comply with 1 kV/mm as specified in IPC-2221. However, worst-case pro- jected peak-to-peak insulation distance includes tolerances for laminate thickness as well as for copper surface profile. A thickness tolerance of 13 µm is specified in IPC-4101 for class C lami- nate with nominal thickness of 4 mil. A maxi- mum copper foil profile of 10 µm is specified in IPC-4562 for a nominal foil thickness of 70 µm. Adding these tolerances can give a project- ed peak-to-peak insulation distance of about 68 µm for a nominal thickness of 4 mil. Likewise, etching tolerances need to be in- cluded when specifying intralayer insulation distances between conductors in-plane of the PCB. Recently, PCB design specified in ECSS-Q- ST-70-12C [3] has been endorsed by the space in- dustry. This standard takes worst-case manufac- turing tolerances into account when specifying voltage rating. Double insulation is a frequent requirement for critical high-voltage signals in space appli- cations. ECSS-Q-ST-70-12 specifies for the first time a set of PCB design rules that combines the use of two individually cured insulators as well as additional margin for voltage rating of criti- cal signals. Furthermore, the ECSS-Q-ST-70-12 specifies the presence of non-functional pads to mitigate the risk of drilling cracks in resin- rich areas and it specifies the use of two sheets of prepreg between copper layers as well as two Figure 6: insulation resistance (log Ω) before and after thermal cycles (Tc) from -65°c to +135°c, showing two failed innerlayers of a comb pattern that appeared to be fiber contaminated. FeAture