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56 The PCB Magazine • August 2015 LATENT SHoRT CIRCUIT FAILURE IN HIGH-REL PCBS continues PCB assembly is on the critical path of satellite integration. F. Electrical Testing Typical electrical testing applied on PCBs by flying probe equipment is specified in IPC- 9252 and is based on an insulation threshold of 10 MΩ, corresponding to level C for IPC class 3. The objective of this test method is to verify electrical design, i.e. the absence of unintended connections in the circuit. For IPC class 3/A this test method is amended in IPC-6012 to 100 MΩ under 250 V bias. The working group specified a new high resistance electrical test method [5] with a 1 GΩ threshold and monitoring of voltage during ramp-up, to determine the quality of the in- sulation and to detect possible imperfections in the dielectric material. The rationale is that contamination between nets can provide a high-Ohmic path that can be detected under high voltage bias and therefore fails this test. The requirement for GΩ insulation resistance is specified in ECSS-Q-ST-70-10C [6] and is sub- stantiated by the typical volume resistivity of 10 8 MΩ-cm, determined on dielectric materials at humid conditions of 90% RH in accordance with IPC-TM-650 2.5.17.1. During recent use of this test method, one PCB manufacturer reported failure of a PCB at 160 MΩ insulation. When the PCB was submit- ted to 250 V sustained for a longer period of 1 minute, the net eventually failed in short cir- cuit. Subsequent analysis and DPA showed par- ticulate contamination in a 4-mil base laminate. Scanning electron microscopy (SEM/EDX) iden- tified the presence of titanium and iron, among others. The high-Ohmic path would have re- mained undetected with other test methods. v. Risk Mitigations at Base Material Suppliers A. Observations on Base Materials It has been identified that various produc- tion processes may contribute to the cleanli- ness level of dielectric insulation of a PCB. PCB manufacturers that are qualified in accordance with ECSS-Q-ST-70-10C [6] are subject to an audit process that assesses the implemented risk miti- gations. This is however not the case for base material suppliers. PCB manufacturers perform sample screen- ing on laminates, they perform in-process screening on etched innerlayers and on prepreg sheets during lay-up, and they perform root FeAture Figure 13: contamination embedded in base laminate on external layers bridging the insulation between pads, at outgoing inspection and after assembly.