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46 The PCB Design Magazine • October 2015 the substrate is the most important component of the assembly, so let's get it right! Points to Remember • To minimize inductance, two conductors (signal traces or ground planes) that carry current in the same direction should be separated. • Two conductors that carry current in the opposite direction (such as signal and ground planes or power and ground planes) should be positioned as close as possible. • If power planes are used as reference planes, then the return current must transverse stitching capacitors in order to jump between ground and power planes. • Use multiple ground planes, where pos- sible, rather than power planes, in the stackup, to isolate signal layers. • Place stitching ground vias close to every signal transition (via) to provide a short current return path. • Spread numerous ground stitching vias around the board to connect the multiple ground planes. • Don't use ground pours on signal layers as this reduces the impedance of nearby traces. If you must, in order to balance copper, separate the signal and pour by 20 mils. • To determine the layer count, start with the route pitch. Technology rules are based on the minimum pitch of the SMT components employed and are basically the largest trace, clearance and via allow- able. Then calculate the stackup required for the desired characteristic and the dif- ferential impedances. • A 10-layer board is similar to an eight layer with the addition of two more em- bedded signal layers. These are used to increase routability and to add planar ca- pacitance. • The methodology I have set out, in previ- ous columns, can be used to construct higher layer count boards. PCBDESIGN References 1. Barry Olney Beyond Design columns: Ma- terial Selection for SERDES Design, Material Se- lection for Digital Design, The Perfect Stackup for High-Speed Design, and Embedded Signal Routing. 2. Henry Ott, Electromagnetic Compatibil- ity Engineering. 3. Lee Ritchey, Right First Time Design. 4. Howard Johnson, High-Speed Digital De- sign. 5. To download the ICD Stackup and PDN Planner, visit beyond design Barry Olney is managing director of in-Circuit Design Pty ltd (iCD), Australia. This PCB design service bureau specializes in board-level simulation, and has developed the iCD Stackup Planner and iCD PDn Planner software. To read past columns, or to contact Olney, click here. STACKuP PLANNING, PART 4 researchers at MiT have created tiny pores in sheets of graphene that have an array of prefer- ences and characteristics similar to those of ion channels in living cells. each graphene pore is less than 2 nanometers wide. each is also uniquely selective, preferring to transport certain ions over others through the graphene layer. To create pores in graphene, the group used chemical vapor deposition, a process typically used to produce thin films. in graphene, the process naturally creates tiny defects. research- ers may one day be able to tailor pores at the nanoscale to create ion-specific membranes for applications such as environmental sensing and trace metal mining. Big Range of Behaviors for Tiny Graphene Pores

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