Issue link: https://iconnect007.uberflip.com/i/586473
16 The PCB Design Magazine • October 2015 feature to visually share information and ask questions to learn what's critical and what's not from the customer, and to facilitate a smooth launch of the design process. We like to request mechanical data from the customer in the form of EMN or 1:1 DXF files that can be imported into the CAD tool. This is more efficient and less prone to error. To assure that electrical rules are followed, we like to get the rules (match groups, max length, spacing for noisy signals, etc.) in a doc file or a spread- sheet so we can enter them into the constraint manager. We also determine if previous designs or sec- tions of the design can be reused. Reuse of a pre- vious board outline, existing stack-up, and PCB fab and assembly drawings notes is a simple way to save time. Reusing prior circuit designs, such as power supplies or DDR routing, can save a significant amount of time. Again, third-party tools such as dalTools and EMA Design Automa- tion's CircuitSpace make reuse in Allegro even more efficient. CircuitSpace can also be used to reduce placement time by AutoClustering func- tional groups of components. We have found that component area place- ment and route studies can be very helpful to identify solutions in problem areas prior to tack- ling the complete board design. These efforts will enable the engineer and designer to work through the tradeoffs that are often required to resolve issues without the distractions of the peripheral items associated with the complete board design. When completed, the results of the placement or route studies can be used in the actual design and provide a faster and more predictable design cycle time to complete the board. An area of communications that is often un- derappreciated, but has become vitally impor- tant to design efficiency, is the dialogue with the PCB fabricator. It's critical to engage the fab- ricator very early in the design process to nail down the proper materials and stack-up. With so many options for via structures, it is critical to select the most appropriate structure for the design. Adding blind and/or buried vias as an af- terthought can limit their utilization and drive up the printed circuit board cost. The designers need to know if back drilling is a requirement in order to plan their routing strategies. We have seen many project timelines impacted by elev- enth-hour negotiations between the engineer and fabricator for stack-ups and line width and spacing approvals. In addition, we highly rec- ommend that the printed circuit board assem- bler be involved early in the process to review the placement file for DFM approval. It's much more efficient to make any component adjust- ments before the routing and delay tuning is implemented. Flow planning is another area that can save time. We use Cadence's flow planner to help plan the routing on the various layers. It allows us to grab a "bundle" of traces and plan their track layer by layer, while taking into account how much room they will require based on their constraints. This provides a couple of ef- ficiency benefits. One, it identifies bottlenecks in the planning stages, and two, the flow plan can be used to provide guidance to the design- ers who are doing the routing to support the lead designer. Signal and power integrity analysis are key methods for assuring that the board design will meet the performance requirements on the first pass. By using software to simulate the effects on signal and power integrity, our customers spend less time in the lab trying to find out why their design isn't performing as expected. Perform- ing in-process simulations enable problems to be identified and corrections to be made earlier in the design process, minimizing the collateral DON'T BE HELD HOSTAGE BY DESIGN CYCLE TIME " We have found that component area placement and route studies can be very helpful to identify solutions in problem areas prior to tackling the complete board design. "