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58 The PCB Design Magazine • November 2015 primary contributor to the number of layers re- quired for routing. An effective fanout solution should provide low inductance supply connec- tivity, minimal cross-over of signals, reduced crosstalk, breakout on multiple layers and layer reduction. The increasing pin count and de- creasing pitch of BGAs proves a challenge to both PCB designers and routing technologies. Placement, orientation of interconnecting de- vices, swapping of I/O pins to reduce crossovers, together with the fanout to internal layers, are also key factors of routability. The design constraints need to be estab- lished before an attempt to route is initiated. These include: 1. Stackup planning: This should be de- fined at the time of design entry to improve signal integrity, reduce crosstalk from adjacent layers and provide clear, uninterrupted return paths for all critical signals. There are many stackup options using a myriad of high-speed materials and these should be chosen based on the pre-layout simulation. The stackup should also be designed based on the technologies in- corporated on the PCB to include all the single ended and differential impedances used. This determines trace width and clearance of each layer for each technology. 2. Via spans: These should be selected based on the stackups construction and the density of the BGAs to provide a fanout to in- ternal layers. Blind and Buried vias need to be considered in order to fanout from 0.8 mm or less pitch BGAs. 3. Signal integrity: SI should be consid- ered early in the design process to eliminate crosstalk, extended return current paths, and EMI. 4. Power integrity: PI should also be analyzed up-front to determine the number and values of bypass and decoupling capaci- tors required to reduce the AC impedance to an acceptable level, given the switching regu- lator properties. Plane resonance should be analyzed to determine the best possible plane definitions. beyond design Design constraints can be established based on the above requirements. These are entered at the schematic level and carried through to the PCB database to control the router. The router needs rules to determine the most effective path but too many rules can also bog it down to such an extent that it will not perform. Care must be used when creating and prioritizing rules. Once the schematic has been completed, the FPGA I/Os need to be evaluated for cross- overs and pins swapped where necessary, to as- sist the router as much as possible. You could do this manually, but it is very time-consuming. Alternatively, Mentor's IO Designer FPGA-PCB co-design tool integrates synthesis and I/O op- timization. To obtain a high route-completion rate, component placement is extremely important. If the board is difficult to route, it may just be the result of poor placement, slots/gates posi- tioned all over the board, or perhaps the se- quence of pins on components are flipped. We need to help the router as much as possible by opening route channels and providing space for vias. In the classic high-speed design flow, timing specifications and simulation results are com- pared to determine placement and routing con- straints. Given a length constraint, a designer can control signal integrity by controlling the PCB trace topology of the various parts of an interface. Included in this topology are any ter- minations. Interactive placement is best done by cross- probing, as in Figure 1, and dragging the com- ponents one by one from the schematic to place on the PCB, taking functionality and de- sign constraints into account. Once the correct placement and orientation of the major devices is complete, the IO Designer can then be in- voked to make some sense of the rats nest. The trend now, is to put control of the au- torout er back into the hands of the designers to enable clean, highly desirable results. The Sketch router can optimize the trace fanouts at both ends of the netlines, avoiding additional vias when completing the routes. It can also gloss the finished route to look much like a manual route. The idea is to give the designer control over the location of the routing, along with some style WHY AuTOROuTERS DON'T WORk: THE MINDSET!