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December 2015 • SMT Magazine 57 Quantify Impact of board Design and Process control on SmT Performance Project Leaders: Sandeep Sane and Ram Viswanath (intel) Status: in formation warpage issues can significantly affect SMT yield. inEMi has ongoing projects focusing on package warpage characterization (description be- low); however, the impact of board design, warp- age, paste print and process temperature on SMT yield is not well understood. This initiative propos- es to study those gaps and investigate board warp- age and its correlation with SMT yield. Ultra Low Loss Laminate/Pcb for High reliability and Performance Project Project Leaders: Gary long and Stephen Tisdale (in- tel); Mason Hu (Cisco) Status: in process This initiative is addressing key technology challenges and measurement capabilities needed to deliver ultra-low loss, high-reliability PCB lami- nate and board performance. options are currently limited for low-cost, high-performance PCB mate- rials capable of high-volume manufacturing (HvM) processing. High layer count/multi-layer construc- tions are becoming increasingly complex with few- er material options. This initiative was organized to close major gaps and evaluate new materials based on electrical and thermo-mechanical capabilities for high-layer-count/multi-layer applications. Test boards are in fabrication at four sites. Electrical and mechanical testing will begin soon. Warpage characteristics of organic Packages, Phase 3 Project Leaders: Wei Keat loh (intel), ron Kulter- man (Flextronics) and Tim Purdie (Akrometrix) Status: in sign-up The influence of package warpage on assem- bly quality and reliability are receiving increasing attention across the industry. in its first two phas- es, the inEMi Warpage Characteristics of organic Packages Project carried out a broad experimen- tal program to characterize ball grid array (bga) package warpage using thermo moiré. The output of the previous work can be found on the project webpages. as the project has gained significant in- terest from industry, the team has decided to con- tinue this effort with a third phase, which plans to: • identify measurement methods and proto- cols based on the different measurement tech- niques and technology, such as: confocal tech- niques, projection moiré techniques, thermo moiré techniques with or without convective reflow, and 3D digital image correlations (DiC). • Benchmark or fingerprint package warpage characteristics to develop a better understanding of the current trends of warpage behavior for dif- ferent package constructions. bi-Sn based Low Temperature Soldering Process and reliability Project Leaders: Raiyo Aspandiar and Scott Mokler (intel) Status: Project plan submitted; expect project start in January Higher energy costs are driving oDMs to re- duce power usage in manufacturing processes and the lower temperatures in reflow ovens can save significant amount of energy. lower reflow solder- ing temperatures can mitigate the warpage impact on solder joint yields (a problem that has been ex- acerbated recently by the burgeoning of ultra-thin electronic packages for slimmer and lighter elec- tronic products with increasing performance). Bi- Sn solder pastes are most appropriate candidates for these lower temperature processes, but Bi-Sn solder is brittle and mechanical/shock reliability of solder joints is not robust enough for mobile prod- ucts. new developments to overcome this draw- back are ductile Bi-Sn solder pastes and joint rein- forced Bi-Sn solder pastes but the effectiveness of these pastes to enhance solder joint reliability has not yet been established. This new initiative is proposed to identify and select available ductile and joint reinforced Bi-Sn solder pastes, develop high yield (>95%) reflow soldering process for a variety of test components and board surface finishes using these Bi-Sn solder pastes, and assess the solder joints' reliability. SmT ineMi's Current Collaborative Projects in the Areas of board Assembly and Packaging FeATure inTerview InemI: LeADInG THe WAy To SUcceSSFUL eLecTronIcS mAnUFAcTUrInG

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