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January 2016 • The PCB Design Magazine 33 pacitor mounting inductance. The ZBC-2000™ laminate is constructed us- ing a single ply of either 106 or 6060 style pre- preg, yielding a dielectric thickness after lami- nation of 2 mils when measured by cross sec- tioning. The ZBC-1000 technology results in a 1 mil dielectric distributed capacitance material. FaradFlex™ and Interra™ buried capacitance products utilize a durable resin system for non- reinforced dielectrics for 1mil thickness and below. This also eliminates the skew associated with the fiber weave effect in standard materi- als. Also, with a product range up to 20nF per square inch in capacitance density, 3M ECM is the highest capacitance density embedded ca- pacitance material on the market. These ultra-thin laminates allow a signifi- cant layer count reduction in PCBs with bet- ter signal performance. Having a low dielectric constant, combined with very high withstand- ing voltage, these glass-free films change the design rules for via diameter and trace width, while still conforming to the manufacturing needs of the Fab shop. Three traces between vias, at a 0.4 mm pitch, are not only possible but very manufacturable according to Integral Technology. It is a common belief that solid power and ground planes act as a large, perfect, lumped element capacitor. However, they actually en- compass a distributed system of surprising com- plexity. The distinction between a lumped ele- ment and a distributed system involves the re- lationship between the time delay of the system and the rise-time of the signals. For instance, for a PCB of six square inches, the signals entrapped between the VCC and beyond design GND planes create a standing wave, resonat- ing as they reflect from side to side, and have a delay time of about 1ns. If the rise time of the signal is 5ns, the lumped condition is satis- fied. However, with a much faster rise time or if the DDR3 plane is very small (typically one inch square), then the driver perceives the VCC and GND structure as a distributed object with significant delay. This delay causes a couple of issues: 1. During the rising and falling edge, only the portion of the planes and decoupling ca- pacitors located within the close vicinity of the driver can react before the edge has vanished. This frequently results in the noise spike being larger than anticipated. 2. The residual PDN noise from the first event reflects like an unterminated transmis- sion line a couple of ns later, back to the driver. If at that precise moment, the driver switches a second time, both pulses (first and second) are superimposed. If the phases add and the driver has a repetitive pulse (as clocks do), the reflect- ed pulse may build significantly. One could possibly avoid this potential fail- ure by comparing the round-trip delay across the plane, in question, to the clock period. If it is close, then an adjustment in plane size may be an appropriate solution. This may not eliminate all plane resonances but can serve to shift the resonances to other frequencies. Also, adding stitching vias, in appropriate locations, can reduce the extent that signal energy spreads through the plane cavity, and raises the fre- quency of structural resonances. PLANE CRAzY, PART 2 Table 1: embedded capacitor materials available in the ICD Dielectric Materials library.