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58 The PCB Design Magazine • January 2016
the via-in-pad fill material, and Q
3
is the heat
flow through the FR-4 material. Several meth-
ods to employ to optimize the flow of heat in-
clude making the via hole diameter (d) as large
as possible to maximize the volume of copper
that composes the via wall (solve for the vol-
ume of a cylinder). Attach as much copper as
possible to as many vias-in-pad as possible on
the inner layers and connect these vias to paral-
lel layers to increase the connected volume of
copper (each additional internal layer contact-
ing the vias will increase the volume available
to dissipate the heat into).
Once the via-in-pad reaches the layer that will
be used to complete the electrical connection,
widen the copper of the trace on the terminating
layer as much as possible so that the developing
heat will have copper to flow into and disperse.
In a CSP package, the thermal resistance of the
silicon substrate should be considered much low
-
er than the thermal resistance of a via-in-pad that
conducts from the component side of the PCB to
any alternate layer; as a result, the CSP package
will be approximately isothermal (give or take a
few degrees) throughout its volume. Therefore,
each CSP pin should be considered equivalent-
ly connected to the heat source and capable of
transferring the same amount of heat from the
IC even if the signal of the pin conducts little
current or is not physically located near a heat-
generating source inside the IC.
With this concept in mind—that each CSP
pin is capable of transferring an equal amount
of heat if connected to similarly sized copper
shapes—every connection to every CSP should
be completed using the maximum area of cop-
per plane or trace that is as thick as possible
(i.e., 2 oz. Cu weight vs. 1 oz.) to improve the
heat-sinking ability of the board.
Figure 3 shows the third layer of the PCB
from the component side of the board, and
each via-in-pad has the surface area of the cop-
per connected and maximized regardless of the
electrical current the trace conducts. The only
traces that are left "thin" are those that are not
in contact with a via-in-pad directly connected
to the IC. These can be identified by the larg-
er-diameter holes (grey circles) verse the much
smaller diameter of the via-in-pad located under
the CSP footprint (small diameter forced due to
the 0.4 mm IC pin-to-pin pitch) which only
allows for 0.254 mm (10 mil) pad and a 0.127
mm (5 mil) diameter (d, from Figure 2) via-in-
pad. In this example layout, the signals for /EN-
ABLE, TS, FOD2 will carry, at most, less than a
micro-amp of current each, but the traces are
purposely widened in order to take advantage
of the heat-carrying capacity of the connection
to the via-in-pad connected to the CSP package.
Reconsidering Equation 1, the heat flow is
influenced by the distance (L) from the heat
source to a heat-spreading plane or layer. Sim-
ple examination of thermal conductivity values
for copper and FR-4 will prove that copper
(thermal conductivity) is superior at transfer-
ring heat compared to FR-4 (thermal conductiv-
ity ); however, when the distance (L or thick-
ness of the dielectric) is much smaller compared
to the area (L<