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44 The PCB Design Magazine • January 2016 quiet power HoW To DESIgN A PDN FoR THE WoRST-CASE SCENARIo Note the enormous increase of noise: From the 100 mVpp value for a perfectly flat imped- ance, the noise went up almost three-fold, even though we stay within the impedance target! Lastly, we show the noise penalty as a func- tion of notch depth. We already showed that the Q value is irrelevant, so we use an arbitrary Q=3 value and set the second-order notch to produce an impedance minimum at 1 MHz with a series of values between no notch (100 mOhm) and 1 mOhm. The impedance profiles are shown in Figure 10, the step responses are shown in Figure 11. The worst-case transient noise for 1A step excitations is shown in Figure 12. Figure 12 clearly shows the penalty of a non-flat impedance profile: for small deviations it varies linearly and proportionally to the max/ min impedance ratio. For a single second-order notch with large deviations, the noise penalty saturates at about 3x. All the above means that very counter-in- tuitively noise goes up substantially even if we Figure 10: Magnitude of a flat impedance with a single second-order notch with different minimum values at 1 MHz. Figure 12: relative noise increase as a function of relative max/min ratio of impedance profile on a flat impedance with a single second-order notch. Figure 11: Step responses of the flat impedance profiles with a single second-order notch with var- ious minimum impedance values from Figure 10. Figure 13: Magnitude of a flat impedance with a single 100 mohm peak at 1 MHz with different minimum values.