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62 The PCB Design Magazine • January 2016 The final and most effective means to lower- ing the operating temperature of a CSP device is to maximize the volume of copper in con- tact with the IC on the component side of the PCB. The component side of the board is the layer that can transfer heat the most effective- ly away from the PCB due to the proximity to the ambient environment. Any inner layer heat must traverse to the PCB surface before it can be dissipated; therefore the surface temperature must be elevated for heat to flow away from the PCB. Another way to analyze the way surface copper will transfer heat most effectively is to compare the ratio of area to length of the heat paths close to the source. The key to identify- ing the most substantial paths is to determine the paths with the largest ratio and the number of these paths should be counted and summed since they are cumulative. This is a way to cal- culate a simple comparable value of potential thermal resistance of individual and cumulative heat transfer capabilities. Considering a 36-pin CSP device that is a 6x6 array, let's assume the IC has 8 GND pins and each is connected directly to GND planes; with the thin via walls and the relatively long distance to the next layer, the ratio of area to length (A/L (m2/m)) is higher when consid- ering the via compared to a 0.254 mm trace connected to a copper shape on the compo- nent side of the PCB. For example, a via that is 0.152 mm diameter via that has a length of 0.47 mm is a cylinder with the area of each in- finitely thin annulus of the cylinder would be ~13.9 nm (assuming a via wall thickness plated up to of 25 µm thick) results in a heat transfer ratio of 29 µ (A/L). Now, calculating the heat transfer ratio of a short component side trace to a heat-spreading plane with a length of 0.254 mm comprised of 1-oz copper and is 0.254 mm wide results in a heat transfer ratio of 35 µ (A/L). The short cop- per trace has a higher ratio and thus will conduct more heat than the via. Now consider that there are 8 GND vias, the total via-in-pad heat ratio would be 280 µ verse 350 µ if the CSP perimeter pins have 10 out of 21 perimeter pins are able to be connected to a wide surface of copper. So component side connections have a larger heat path ratio and typically have more direct con - nections to heat-spreading surfaces available than the number of vias-in-pad that are avail- able for direct connections to copper planes. Operating temperature is the result of the ambient temperature plus the increase in tem- perature needed to displace and dissipate all heat generated. Optimal thermal performance is achieved by designing a PCB that has the generated heat from the CSP spread as evenly as possible to as wide of an area as possible by conduction, so that convection is maximized by forcing the smallest possible delta from IC package temperature to the PCB surface tem- perature to ambient environment temperature. Since the CSP power devices do not have a di- rect substrate to PCB connection (such as the E-PAD of QFN packages), the flow of heat must be considered on a pin-by-pin basis. For the CSP, the heat path from each pin to the substrate is nearly identical since the die will be nearly the same temperature (within 1–2°C); therefore, each pin connection should be carefully inspected to increase copper con- nectivity in order to optimize the heat transfer from the integrated circuit to the PCB under development or revision. Since the component side of the PCB is the most effective means of heat transfer due to the outer pins having no thin vias, and there is a large number of outer perimeter pins all outer perimeter pins should have wide copper shapes connected to them as space permits regardless of current flow on the node without neglecting current carrying requirements. Finally, vias-in-pad should be uti- lized to connect each inner pin to wide copper shapes or traces as space permits, multiple lay- ers decreases operating temperature as well as thinner PCBs. PCBDESIgN References 1. Resnick, Robert. "Physics, 5 th Edition, Vol. 1," Wiley, 2002. ENHANCINg THERMAL PERFoRMANCE oF CSP INTEgRATED CIRCuITS Nicholaus Smith is an applications engineer at Integrated Device Technology. article