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April 2016 • The PCB Design Magazine 41 as high as possible. With conventional T-topolo- gy, the trace stub is lengthened with an increase in the number of memory device loads. In some cases, there can be as many as eight memory devices connected to the processor. The reso- nant frequency or bandwidth is inversely pro- portional to the stub length. where fo is the resonant frequency, c is the speed of light and Er is the dielectric constant The clock traces should be routed to a longer delay than the strobe traces per byte lane. This is necessary because: 1. The write leveling is capable of adjusting the clock to write data strobe alignment over a wide range, assuming the clock trace has a lon- ger delay than the strobe traces. 2. The read leveling is capable of adjusting the read data eye to read the data strobe over a wide range. The adjustment is per byte, so board skew between the data and data mask sig- nals should be minimized. 3. There is no automatic training for align- ing command/address signals to the clock, but a fixed offset is programmable, in the proces- sor, and can be used if necessary. Skew between the clock and address/control signals should be minimized. Designing a memory interface is all about timing closure. Each signal's timing needs to be compared to the related clock or strobe signal in such a way that the data can be captured on both the rising and falling edge of the strobe—hence the term double data rate (DDR). The increase of data rates, to 4266MT/s for DDR4, has made the timing margin associated with each rising and falling edge much tighter. Even though a direct successor is not currently planned, sourc- es speculate that the 5 th generation DDR5 will use a serial interface to eliminate the issues as- sociated with parallel busses. Serial busses are easier to scale up and have fewer connections, making PCB design less demanding. It seems that every datasheet or reference standard you read on DDR design quotes dif- ferent allowances for the timing budget. At a basic level, the differential clock is the reference signal for the address/control and command Table 1: example of the overall DDR3-1066 timing budget allowances and resulting margin. DDr3/4 fLy-By vs. t-topoLogy routing