44 The PCB Design Magazine • April 2016
layers 1 and 4 is a massive 54ps—way outside
the setup margin.
Whilst stripline layers 3 and 4 have an 11ps
difference, even though they are routed to the
same length. This is due to the variance in di-
electric constant of each layer which changes
the velocity of the signals propagation. The
difference is graphically displayed in the ICD
Stackup Planner's new Relative Signal Propaga-
tion dialog. Even the 11ps stripline variance is
more than enough to offset the timing, particu-
larly using high-speed DDR3 and DDR4 devices,
regardless of the routing topology.
In conclusion, fly-by topology supports
higher frequency operation, reduces simultane-
ous switching noise, reduces the quantity and
length of stubs and consequently improves sig-
nal integrity and timing. And, most important-
ly, from a PCB designer's point of view, it eases
routing of memory devices dramatically. How-
ever, no matter what topology is implemented,
one should pay strict attention to the signal
propagation, on each layer, ensuring the total
flight time of the critical signals match, regard-
less of length.
Points to Remember
• Fly-by topology supports higher frequency
operation, reduces simultaneous switching
noise, reduces the quantity and length of
stubs and consequently improves signal
integrity and timing.
• The controller must add the write leveling
delays to each byte lane to maintain the
strobe to clock requirement at the SDRAMs.
• T-topology can be challenging to route but
it can be advantageous when using multi-
die packages with high capacitance loads.
Whereas, fly-by topology eases routing of
DDR3/4 devices.
• The double T-topology was used for DDR2
and had a downside in that the impedance
discontinuities, due to branching along
the traces, caused obvious margin losses.
• With conventional T-topology, the trace
stub is lengthened with an increase in
number of memory device loads.
• The clock traces should be routed to a lon-
ger delay than the strobe traces per byte
lane.
• Designing a memory interface is all about
timing closure.
• The portion of the timing budget, con-
sumed by the controller IC and SDRAM
devices are fixed and cannot be influenced
by the PCB designer.
• If you work on 10ps, then you can be as-
sured you are within the margin allowing
for any derating.
• The margin limits can be increased, if the
memory interface is not operating at the
maximum frequency and/or if a fast mem-
ory device is used.
• Matched length does not equal matched
delay. The most dramatic difference being
that of microstrip (outer layers) to stripline
(inner layers).
PCBDESIGN
References
1. Barry Olney's Beyond Design columns:
PCB Design Techniques for DDR, DDR2 &
DDR3 Parts 1 & 2; Matched Length does not
equal Matched Delay
2. JEDEC Specifications JESD 79F, JESD79-
2E, JESD79-3F & JESD79-4
3. The Xilinx Zynq-7000 PCB Design Guide
4. EDN article by Chang Fei Yee: DDR4
memory interface; Solving PCB design chal-
lenges
5. Micron's TN-41-08: Design Guide for Two
DDR3-1066 UDIMM Systems Introduction
6. The SI List, available at Freelists.org
7. The ICD Stackup and PDN Planner soft-
ware can be downloaded from www.icd.com.au
Barry Olney is managing director
of In-Circuit Design Pty ltd (ICD),
Australia. This PCB design service
bureau specializes in board-level
simulation, and has developed the
ICD Stackup Planner and ICD PDn
Planner software. To read past
columns, or to contact Olney, click here.
DDr3/4 fLy-By vs. t-topoLogy routing
