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74 SMT Magazine • July 2016 Based on warpage measurement defined by JESD22-B112A 8 , the PoP package warpage can be extracted from just the BGA region along the pe- ripheral edge of the PoP memory package. The peripheral warpage magnitude, as shown in Fig- ure 5, was generally lower than the entire pack- age area, as expected due to the smaller area of interest. The benefit of analyzing peripheral BGA warpage provided some perspective of which re- gion of the package contributed the most warp- age. For example, PoPmB5 had ~50 µm warpage for the entire package area, while <20 µm for the peripheral BGA warpage at elevated temperature. This shows that the region without BGA balls contributed part of the warpage magnitude. For PoPmB7, both package area and BGA area had approximately the same level of warpage. Depending on the engineering assessment needed, the entire package area warpage plays a more critical role in PoP stack-up assembly be- cause it gives better insight into any geometrical interference with PoP bottom package. Howev- er, the coplanarity specification in JEDEC Pub- lication 95 2 only calls for measurement of the BGA area coplanarity, which may subject am- biguous correlation to PoP component board assembly yield. As for the effect of preconditioning on PoP memory warpage, Figure 6 shows the interac- tion of room temperature and peak reflow tem- perature warpage magnitude as a function of as is, bake and MET 9 days. The room temperature warpage for PoPmB4 and PoPmB7 was affected by bake and MET preconditioning. PoPmB7 ex- hibited 50 µm increase in room temperature warpage while exposure to moist environment reduced the warpage. This could be due to stress relaxation that occurred during baking while the package swelled when exposed to a moist envi- ronment. However, the warpage at high tempera- ture was not impacted among the PoP memory considered. This seems to suggest that baking- and moisture-induced warpage changes have less impact on thin packages at high temperature. Package Warpage Qualification Improvement Opportunity Based on the warpage data collected, the iN- EMI project team has a fundamentally broad da- taset to analyze further with respect to warpage qualification assessment. The reporting format for package warpage outlined in JESD22-B112A 8 and data reported elsewhere typically used a few samples due to limited resources and other specific constraints. When addressing board as - sembly yield-related issues, the limited sample used for dynamic warpage measurement may or may not explain the corresponding yield per- Figure 5: PoP memories package warpage for various designs. (Measurement area: BGA area only.) PACKAGE-ON-PACKAGE WARPAGE CHARACTERISTICS AND REQUIREMENTS