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76 SMT Magazine • July 2016 assembly yield. This is because most of the yield lost may be due to extreme warpage character- istics that may not have been captured by using only a few samples. The data collected here re- quires further analysis to enhance the warpage qualification method. SMT References 1. JEDEC Publication 95 Design Guide 4.22, Fine-pitch, Square Ball Grid Array Package (FBGA) Package-on-Package (PoP). 2. JEDEC Publication 95 Design Guide 4.5 Fine-Pitch Square Ball Grid Array Package & Fine-Pitch Interstitial Square Ball Grid Array Package. 3. Design Standard 4.6 Fine-pitch, Rectangu- lar Ball Grid Array Package. 4. JEDEC Publication 95 Design Guide 4.17 BGA (Ball Grid Array) Package Measuring and Methodology. 5. Hamid Eslampour, Mukul Joshi, Seong- Won Park, HanGil Shin, JaeHan Chung, "Ad- vancements in Package-on-Package (PoP) Tech- nology, Delivering Performance, Form Factor & Cost Benefits in Next Generation Smartphone Processors," Electronic Components and Tech- nology Conference, 2013, pp. 1823–1828. 6. Dongji Xie, Dongkai Shangguan and David Geiger et.al., "Head in Pillow (HIP) and Yield Study on SIP and PoP Assembly," Electron- ic Components and Technology Conference, 2009, pp.752–758. 7. Ken Chiavone, "Analyzing Package-on- Package (PoP) Reflow Assembly Interfaces with Interconnect Gap Analysis", 36th International Electronic Manufacturing Technology Confer- ence, 2014. 8. JESD22-B112A Oct 2009, "Package Warp- age Measurement of Surface-Mounted Integrat- ed Circuits at Elevated Temperature," October 2009. Wei Keat Loh is the thermal me- chanical fluid core comp manager at Intel Malaysia. He is also the chair of Warpage Characteristics of Organic Packages Project. Haley Fu is the manager of opera- tions for Asia at iNEMI. Figure 7: Effect of sample size used for dynamic warpage characterization. PACKAGE-ON-PACKAGE WARPAGE CHARACTERISTICS AND REQUIREMENTS