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12 The PCB Design Magazine • July 2016 1. Introduction Simulation advancements released over ten years ago [1,2,3] allowed examination of serial links in greater detail, identifying performance limit- ers [4, 5] which motivated further refinements in the same [6] . Once tuned, the technologies were scaled to rapidly scan thousands of serial links to identify failure modes in rogue channels [7] enabling their correction and confident tran- sition into production using simulated bit er- ror ratios (BERs) as a qualifying metric [8] . This paper leverages and enhances these same tech- nologies to provide large-system SerDes setting optimization and cost reduction, highlighting recent advancements in equalization optimiza- tion techniques and algorithms. SerDes setting optimizations are applied to a wide range of channels across systems of various sizes. Optimization techniques are de- scribed, automated, applied to thousands of links and performance gains are quantified. SerDes tuning processes were simpler when one or two taps were available in the Tx and the Rx equalization options were few. However, with by Donald Telian, SIGUYS, and Michael Steinberger, Barry Katz, SISOFT This paper was originally published in the proceed- ings of DesignCon 2016. Abstract Large systems with multiple configuration options and extended product lifecycles pro- vide performance tuning opportunities such as SerDes setting optimizations and manu- facturing improvements. This paper describes newly-developed techniques for equalization tuning and discontinuity reduction, offering additional design margin. Cost reductions are also achieved as new signal integrity (SI) tech- niques demonstrate performance parity remov- ing non-essential re-timers and PCBs layers. This is the fourth in a series of DesignCon pa- pers detailing the design and implementation of a system characterized by multiple thousands of interconnected serial links spanning dozens PCBs, operating at 3rd and 4th generation serial link data rates (6 to 12 Gbps). FEATURE New SI Techniques for Large System Performance Tuning

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