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July 2016 • The PCB Design Magazine 33 tinue once a netlist is ready and loaded into a layout-based application. This is really where design specific SI analysis can and should start even before any routing. Why? There's an obvious goal of reducing the overall effort required for SI signoff and there's plenty that can be analyzed prior to the routing even starting. Let's take a look at what we typically concern ourselves with in the SI domain. We have signal quality with challenges like overshoot and ringback, timing-related is- sues like delay, what kind of routing topology works best for the situation and whether or not termination is needed, and of course crosstalk. The only one of these that absolutely requires routed traces in place is crosstalk. This represents an ideal time to simulate the entire design, and in particular the interfaces that were not captured and simulated with to- pologies, for any of those SI issues, with the ex- ception of crosstalk. Device model data assign- ments have propagated to the layout database as part of the netlist and simulating with un- routed nets will be quick since the interconnect is represented with a simple ideal model based on Manhattan distance and an impedance. In some cases, the Manhattan distance can be re- placed with design data to give a more accurate estimate of how certain nets will be routed. This can be useful at the pre-route stage to improve the accuracy of SI analysis. Floorplanning stage analysis can lead you to placement edits or changes which are too pain- ful after investing any time in routing. This is another example of where the constraint sys- tem and SI analysis leveraging the same design data can improve the overall process. Screening At this stage of the design, the focus is rule checking. Constraints and rule checking will drive any automated or manual routing with DRC violation feedback from the rules devel- oped and implemented in the earlier stages. This traditional constraint-driven design meth- odology was born roughly two decades ago. Over the same time, data rates have gone from tens of Mbps to several Gbps for parallel inter- faces plus we've seen the dawn of serial inter- faces with even higher data rates. As a result, Figure 3: Example of a design with nets represented in bundles to guide routing. SIGNAL INTEGRITY TOOLS AND DESIGN METHODOLOGY IN THE MODERN AGE

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