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34 The PCB Design Magazine • July 2016 DRCs now share the screening limelight with ERCs (electrical rule checks) and SRCs (simu- lated rule checks). As these names imply, they involve more than just traditional physical rule checks and rely on some of the same data we use for traditional SI analysis. This represents an ideal time for the layout designer to catch as many potential SI issues be- fore any post-layout analysis. Impedance and coupling can be checked and resolved without the need for any complicated setup or analy- sis. Results can be more than simple violation markers to provide better visual clues to viola- tions and areas that need attention. The most critical thing to consider for to- day's designs is how power and signal interac- tion affects signal integrity. As the design pro- gresses and PDN structures such as planes are implemented, coupling among power nets, signals, and vias can and should be evaluated. Many constraints are formed at the early stages of a design before planes and vias exist. Perform- ing physical rule checking as these elements are added should not be based on the assump- tion of ideal planes. Impedance, trace coupling, crosstalk, delay, and skew need to account for the impact of power noise upon signals. This new breed of SRCs performs analy- sis of signal and power coupling by applying a linear excitation to large number of signal nets. These SRCs report signal quality includ- ing all coupling noise while avoiding any time consuming non-linear simulation. The results guide layout designers to find issues general post-route rule checking, assuming ideal refer- ence planes, cannot find. One example of this is where via coupling from a plane can induce crosstalk that increases as the traces are sepa- rated. This seems to violate not only common sense but also any traditional crosstalk rule that relies on ideal reference planes. It can only be captured when plane noise and via coupling are considered. At this stage the device models assigned in the layout may not get exercised for each type of DRC, ERC, or SRC but it can be very advan- tageous if the same analysis engines and accu- rate solvers used for SI analysis can be accessed by the rule checking. We will examine some of these advanced engines in the next section. Figure 4: Overlays and plots can provide better visualization of constraint issues. SIGNAL INTEGRITY TOOLS AND DESIGN METHODOLOGY IN THE MODERN AGE