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36 The PCB Design Magazine • July 2016 Detailed Simulation With the board-level screening passes com- pleted, the design DRC-clean, and no signifi- cant reflection or crosstalk issues remaining, it is time to focus on the final stage of analysis. This typically involves detailed simulation to per- form compliance analysis for the multi-gigabit interfaces in the design. These will commonly be DDR memory and serial link interfaces, with protocol-specific criteria to be evaluated. Assuming analysis began in the pre-layout stage, this largely consists of performing de- tailed interconnect extraction of layout, replac- ing the "postulated" pre-layout W-element and via models with extracted S-parameters, and re- running simulation/compliance checking for final design margins. For today's DDR interfaces, the power dis- tribution network (PDN) needs to be extracted along with the signals, to account for non-ideal power effects, such as simultaneous switching noise (SSN). The most practical way to do this today is with a "hybrid" electromagnetic (EM) solver, which decomposes copper structures into vias, transmission lines, and shapes, solves them with application-specific solvers, and recom- bines the overall result into an S-parameter model. Including non-ideal power effects into DDR simulations prevents potential problems from being masked by ideal plane assumptions. The extraction for high data-rate serial link interfaces must also be done with care and re- quires even high levels of accuracy. While uni- form PCB traces can be modeled nicely with today's 2D field solvers, the via arrays used for layer transitions will usually require full wave 3D extraction for accurate representation. Figure 5: An SSN simulation. Figure 6: Signals assuming ideal power (top) vs. non-ideal power (bottom). SIGNAL INTEGRITY TOOLS AND DESIGN METHODOLOGY IN THE MODERN AGE