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July 2016 • The PCB Design Magazine 47 tential exists for this area to function like an antenna and generate unwanted radiation. In addition, lack of reference path vias may cause longer return loops and also contribute to in- creased simultaneous switching noise. The rule checker checks to see whether or not padstacks are distributed in the plane with sufficient den- sity. It operates by marking off sections within a user-defined radius of the center of each via. The sections that have not been marked off are considered to be problematic and when the ra- tio of problematic to good sections reaches a specific level in an area, then that area is called out by the rule checker. The SI checker also identifies many other mistakes that might be made in the design lay- out such as track resonance, EMC incompatible layer stack, isolated copper areas, overlapping power planes, high power plan impedance, etc. After running the selected rules, results are pre- sented to the user in a graphical histogram. This also shows the results as a percentage perfor- mance rating and uses a custom color code to reflect the seriousness of the problem. Once the rules have been run, the issues that have been detected can be highlighted in the PCB design. Complete control of the highlighting is avail- able for any combination of rules and design items within the rules. Conclusion The benefit of performing layout-level SI checks is that the need to iterate through time- consuming model extraction and simulation is reduced, as the simulation will identify far few- er SI issues or perhaps none at all. By identify- ing SI issues early in the design process when they can be corrected in much less time and at a much lower cost than after the design has been completed, upfront SI checking can reduce time to market and engineering costs. PCBDESIGN Narayanan TV is a solutions archi- tect at Zuken USA where he helps define chip/package/board co-design solutions with a focus on signal and power integrity. "Nothing is impossible!" In line with this motto, physicists from the Quantum Dynamics Division of Professor Gerhard Rempe, director at the Max Planck Institute of Quantum Optics, managed to realise a quantum logic gate in which two light quanta are the main actors. To realise a universal quantum computer, it is necessary that every input quantum bit can cause a maximal change of the other quan- tum bits. The practical difficulty lies in the spe- cial nature of quantum information: in con- trast to classical bits, it cannot be copied. The realisation of a deterministic photon-photon gate has been a long-standing goal. One of sev- eral possibilities to encode photonic quantum bits is the use of polarisation states of single photons. Two independently polarised photons impinge, in quick succession, onto a resonator which is made of two high-reflectivity mirrors. The resonator amplifies the light field of the impinging photon at the position of the atom enabling a direct atom-photon interaction. As a result, the atomic state gets manipulated by the photon just as it is being reflected from the mir- ror. This change is sensed by the second photon when it arrives at the mirror shortly thereafter. After their reflection, both photons are stored in a 1.2-kilometre-long optical fibre for some mi- croseconds. Meanwhile, the atomic state is mea- sured. The case when the input polarisation of the two photons is chosen such that they influence each other is of particular interest: Here the two outgo- ing photons form an entangled pair. The scientists envision that the new photon-photon gate could pave the way towards all-optical quantum infor- mation processing. Quantum Processor for Single Photons GETTING SIGNAL INTEGRITY RIGHT BY DESIGN

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