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54 The PCB Design Magazine • August 2016 1GHz and become an issue at around 4–5GHz in most cases. This attenuation limits band- width. Figure 2, illustrates the impedance of a standard PTH via compared to a back-drilled via stub as displayed on a Time Domain Reflec- tometer (TDR). In the case of a high-speed back- plane, the effects are even more dramatic as the Nyquist frequency can be in the order of 5GHz, for a 250-mil substrate, and the impact can be evident at 1GHz. As mentioned, vias can appear as capacitive and/or inductive discontinuities. These para- sitics contribute to the degradation of the sig- nal as it passes through the via. One approach is to break each segment of the via into small discrete inductance and capacitance elements corresponding to each section of the barrel in- teracting with the planes and with each other. With this method, it is difficult to achieve an accurate result because the fields are inherently fringe field dominated. Also, matching discrete elements to overlapping fringe fields is difficult. Figure 3 shows a simplified lumped LC p model (without non-function pads) to illus- trate via capacitance and inductance affects. Although this model is only applicable if the delay of the via is less than 1/10 th of the signal rise time, it is still useful for understanding the capacitance and inductance affects. The attenu- ated phase-shifted signal (red) shows the degra- dation effects of the via stub, whereas the back- drilled via (blue) has an undistorted, broader signal. Channel discontinuities can emanate from several sources and each of these must be care- fully considered. One commonly overlooked cause is the signal via. Vias can add jitter and reduce eye openings that can cause data to be misinterpreted by the receiver. Length is the primary factor that influences the inductance of the via, which depends on the design complex- ity, the number of layers, and hence the overall PCB thickness. The length of the PTH via is the same as the overall thickness of the PCB. A typi- cal high-speed PCB design ranges from 1.0 mm to 1.8 mm. For more complex designs, back- planes and military rugged applications, the PCB thickness can go above 3 mm. Given the increasing complexity of high-speed digital de- sign, PCB thickness is expected to increase due to higher layer count. In order to mitigate the effects of the via stub, we need to: HOW TO HANDLE THE DREADED DANGLERS, PART 1 Figure 3: Simplified LC Pi model of via with and without the stub simulated in HyperLynx.