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32 The PCB Magazine • November 2016 LAYER_N-1' using only a blind-via to keep the 'loop area' small. The power mesh architecture was derived from the Interconnected Mesh Power System (IMPS) developed and patented in the 1990s by the High Density Electronics Center (HiDEC) of the University of Arkansas, Fayetteville, AR [9] . Power mesh architecture is the result of ap- plying IMPS lessons to the common microvia multilayer. A four-layer structure is used for the printed circuit. Only power is meshed on the innerlayers because ground is on the outerlay- ers along with via-in-pad technology as shown in Figure 13c and 13d. This reduced layer count microvia multilayer is so efficient in layout, it can replace three times (3x) the number of normal signal innerlayers on a conventional through-hole multilayer and the power and ground planes they require. The table in Figure 13e shows the values for 50 ohm single-ended and 100 ohm differential impedances for different trace widths, spacings, core thicknesses and overall thicknesses. The crosstalk model indicates that the power mesh architecture creates a naturally low crosstalk condition. Each signal trace of 5 mils is approximately 3x or 4x distance from the next signal, depending on the power trace width. This creates horizontal crosstalk of less than 2%. The wiring models used to predict actual wiring density are presented in the Power Mesh article [8] and has 17 to 40 signal inches per square inch per layer while the convention- al through-hole multilayer will have 5 to 12 signal inches per square inch or is 3x to 4x more dense. Conclusion These four techniques can all increase densi- ty and have been proven in volume production. They are relatively old (>20 years) techniques, but can still be used today. Looking for ways to increase multilayer density and reduce layer count, but not reduce the trace width or trace spacings, leave all of these techniques open for new innovations. PCB References 1. Hirai, Osamu, "The Development of Ad- vanced Cu-Plated Through Hole PWB With Landless Vias," Printed Circuit World Conven- tion IV, Session 58, June 5, 1987, Tokyo, Japan. 2. Goosey, M. & Wilkinson, G., "Manufac- ture of Advanced Interconnects," Future Cir- cuits International-Vol. 5, 1999, pp. 181-185. Table 3: Properties and curing processes for the Ormet type of TLPS conductive pastes. INNOVATIVE USE OF VIAS FOR DENSITY IMPROVEMENTS