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80 SMT Magazine • December 2016 tional board test by the latest standards, such as IEEE1687 [8] and IEEE1149.1-2013 [3] . The princi- ple is actually quite easy to understand and is based on the use of JTAG as a transfer medium (Figure 6). In practice, there are no limits to the vari- ety of such instruments. The use of FPGA-based instruments is of particular interest in this con- text. They are temporarily loaded into the target as Soft IP and can be individually customized to the test task. Examples of such instruments in- clude frequency meters, memory testers, bit er- ror rate testers, LAN testers, flash programmers and logic analyzers, to name but a few. In the case of FPGAs, however, there is always the prob- lem that the IP must be individually custom- ized to the corresponding pins of the circuit to be tested. But recent developments such as the ChipVORX technology [9] developed by Goepel electronic even automate this IP to pin contact without requiring a recompilation of the design. The use of external I/O modules with FPGA (Figure 7) is also of interest in this context. They directly expand the use of FPGA embedded in- struments for the functional board test through access to the natural connectors. The third process previously listed in Table 2 is the embedded operating system for testing and diagnosis. Here too, the processor is used as a test executor, however this time it is con- trolled by a complete test and diagnostic soft- ware, such as JEDOS (Figure 8). The software also includes already precon- figured test vectors, and diagnostic algorithms, which are basically executed in real time. The vector download is completely eliminated. This is the final step towards a fully integrated ATE for functional testing. BOUNDARY SCAN MEETS FUNCTIONAL TEST Figure 6: Control of instruments embedded in the chip. Figure 7: ChipVORX I/O module by Goepel electronic with on-board FPGA.