Issue link: https://iconnect007.uberflip.com/i/759357
December 2016 • The PCB Magazine 77 few years printed circuit packaging has taken a jump in sophistication. Not only is surface mounting now very fine pitch, but ball grid ar- rays, flip chip and chip scale packages have en- tered the picture. Take all of this and the many high-density interconnect structures (microvia or buildup PCBs seen in Figure 3) [3] available on the market and design has become extremely complex indeed! Many companies are working on this problem and the program is universally known as DFM/A. But these focus on separate domains: • Optimization of PC design and layout [4] • Minimization of PC substrate costs [2] • Minimization of assembly costs [1] • Use of preferred parts [5] • Analysis of test coverage [6] What they all have in common is metrics. But the design community is suspicious when the entire system is not being considered. They are afraid of sub-optimization, where the cost of a particular domain is lowered but the total sys- tem cost goes up. The design community needs a software environment to integrate all these separate programs. Common Metrics of DFM/A The metrics that have been developed for DFM/A occur in three domains: • PWB layout • PWB fabrication • SMT assembly and test PWB Layout The standard (and not so standard) metrics used prior to PWB layout are: • Packaging Technology Map—A simple technique exists to predict a printed wiring board's wiring factor (WF) and its assembly com- plexity (leads per square inch). The technique is the packaging technology map [7] . By plotting parts per square inch against average leads per part on a log-log graph the WF in inches per square inch and assembly complexity can be calculated. PWB Fabrication The metrics for PWB fabrication deal with tradeoffs between the performance objectives and the PWB prices. This is where producibil- ity came in, since prices need manufacturing UNDERSTANDING PREDICTIVE ENGINEERING Figure 3: Process flow for the design planning of a printed circuit.