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52 The PCB Design Magazine • June 2017 has to deal with, straight from the FPGA place and route tools. To make this more routable, the designer needs to adjust the pin assignment to firstly, be on one outer edge of the BGA. And secondly, order the pins to eliminate crossovers. The connections in Figure 3 use the modi- fied pin assignments displayed in Figure 2 which eliminates the crossovers making the FPGA I/O signals much easier to route, with fewer vias and fewer layers. This in turn improves the sys- tem performance, reduces manufacturing costs and time to market. The problem now is how to back annotate this modified BGA pin assignment to the FPGA design tools? The manual process is time con- suming, tedious and error prone. The key is- sue is to ensure consistency between the tool sets used in the hardware description language (HDL), FPGA and PCB environments. The lan- guage-based HDL representation of the FPGA must be properly represented as a schematic symbol containing the correct pin data, as well as the appropriate mapping to the BGA foot- print. Alternatively, I/O optimization tools can provide parallel paths of FPGA and PCB design, trimming weeks from the design process and implementation schedules and providing sig- nificant overall cost benefits in the long term. These challenges can be met with such tools as Mentor Graphics' FPGA-PCB optimization FPGA PCB DESIGN CHALLENGES Figure 2: Original pin assignment (left) and modified pin assignment (right). Red is the I/O. Figure 3: Crossovers are eliminated by modifying the pin assignment.