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June 2017 • The PCB Design Magazine 53 technology that adds hardware description lan- guage (HDL) synthesis and advanced FPGA-PCB I/O optimization to PADS Professional software. This interface, between the HDL design envi- ronment and the physical implementation on the PCB, significantly reduces both time to mar- ket and manufacturing costs by automating the process, reducing errors and thus iterations. Figure 4 illustrates the synchronization pro- cess. Essentially, once the FPGA design is com- pleted, the pin assignment from the place and route tool is exported to the FPGA-PCB Co-De- sign software. A schematic symbol is automati- cally generated, with this pin assignment, and added to the schematic. The completed sche- matic is then forward annotated to the PCB layout software. The BGA pin assignments can then be optimized to eliminate cross-overs and then back annotated, via the interface, to the FPGA tools. This synchronizes the FPGA pin as- signment to that of the BGA footprint. I/O optimization needs to be tightly in- tegrated with the PCB design flow and be ac- cessible at any stage of the project. Schematic, PCB layout and FPGA databases should always be synchronized which provides user control of the project's design data flow. An FPGA vendor-neutral design environ- ment that enables architecture-specific optimi- zation takes advantage of the specific features for each FPGA device to meet the design require- ments. Vendor-independent synthesis supports FPGA PCB DESIGN CHALLENGES Figure 4: Synchronizing the FPGA and PCB flows.