Issue link: https://iconnect007.uberflip.com/i/869081
September 2017 • SMT Magazine 59 Lastly, a reball recipe was created. The pre- form-package weight stack-up was placed on a fiberglass-resin fixture, and a thermocouple was mounted between the preform and the fixture. Top and bottom heater settings were adjust- ed until the package achieved the critical time and temperatures for soak and reflow. Figure 11 shows the WLP temperature profile during re- ball, with a ~240°C peak reflow temperature. Due to the low mass of the weight and WLP, the reball stack-up blew away during several reball attempts. Consequently, the air flow had to be reduced at the beginning and end of the reci- pe. Optical inspection showed the balls proper- ly wetted to the under-bump metallization, as shown in Figure 12. No opens or shorts were visible on any of the inspected units. CSAM and optical inspection were per- formed before and after the rework process. No thermal artifacts were found, but the follow- ing two mechanical artifacts were observed on multiple units: 1) peeling and chipping of the backside protective tape, and 2) chipping of the dielectric and top metal layers. Figure 13 a,b shows representative CSAM images of the pack- age backside, captured before demount and af- ter reball. Following reball, damage was detect- ed at the interface between the backside pro- tective tape and bulk silicon. Optical imag- es confirmed that the backside protective tape chipped off and exposed the silicon, as shown in Figure 13c. Following a step-by-step inves- tigation, it was determined that the backside protective tape was peeling and chipping af- ter storing and removing the WLPs from adhe- sive packs. Though the tape chipping is cosmet- ic, care should always be taken to reduce arti- facts and prevent masking of the true failure sig- nature. Accordingly, the backside tape artifact was eliminated by storing subsequent samples in plastic trays instead of adhesive packs. Frontside chipping was also detected dur- ing optical inspection. Figure 14 a and b reveals ~50 µm chips near the dielectric and top lay- er metallization. The chips were approximately the same diameter as the tips of fine point met- al tweezers used during WLP handling. Chipped WLPs failed subsequent component-level test, suggesting that the artifacts affected the pack- age integrity. Thus, the results show that front- REWORK AND REBALL CHALLENGES FOR WAFER-LEVEL PACKAGES shows a representative microscope image of one of the desoldered WLPs. Inspection showed the recipe provided adequate solder removal, with only a thin layer of solder remaining on the un- der-bump metallization. Figure 11: Graph showing the package tempera- ture as a function of time during preform reball. Figure 12: Representative microscope image showing WLP after successful reball.