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60 SMT Magazine • September 2017 side chipping can not only mask the true failure signature but also induce failures during com- ponent-level testing. All further chipping was eliminated by handling WLPs with a vacuum pen and plastic tweezers. Table 1 summarizes all the rework-related challenges and risks dis- cussed in this paper, and lists the implemented solutions. Conclusion Rework and reball recipes were successfully developed for board-assembled WLPs. OM and CSAM inspection were performed to evaluate the rework and reball process yield, and screen for thermally or mechanically-induced artifacts. The risk for mechanical damage was minimized by thermally demounting the WLPs with a vac- uum pick-up tube and soft vacuum cup. Tem- perature was well-controlled using a no-con- tact vacuum scavenge technique to desolder the package. Lastly , the WLPs were reballed using a solder preform and a small metal weight. CSAM and OM did not reveal any thermal artifacts dur- ing the rework process, but chipping artifacts were found on the backside protection tape and near the dielectric and top layer metallization. WLPs with frontside chips failed subsequent component-level testing, showing that small di- electric and metal defects can sacrifice electri- cal functionality. Both backside and frontside chipping artifacts were successfully eliminated by improving handling and storage techniques. By implementing similar rework and reball improvements, the industry will be prepared to support WLP FA while maintaining the true defect signature. SMT References 1. TechSearch International Inc., "The Future of Packaging and Assembly Technology," 2016. Figure 13: CSAM images showing (a) the package backside before demount, and (b) after reball. An optical image (c) shows chipping of the backside protective tape. REWORK AND REBALL CHALLENGES FOR WAFER-LEVEL PACKAGES