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16 The PCB Design Magazine • September 2017 PREDICTIVE ENGINEERING: HAPPY HOLDEN DISCUSSES TRUE DFM mation assembly, the product will still be re- leased, but you've got to go to the Philippines, or you've got to go to Vietnam or Indonesia and supervise the manual assembly of that, which to a Japanese engineer is like the worse punish- ment you could even possibly give—to have to go down to Indonesia and supervise 8,000 women building your product. The Japanese nearly kill themselves in order to simplify these things so that the automatic systems can assemble them. Because DFM and DFX is known by everybody, but is caught up in conjunction with design rule checking, and nobody envisions what it would look like if it was predictive, online or before you start de - signing this thing so that we're not going to make mistakes. It's going to be easy to manu- facture. Barry Matties: Do the PCB designers of today consider the automation factor? Holden: No, they don't. Shaughnessy: I don't think so, no. I don't think PCB designers consider themselves part of the manufacturing process at all. But you believe they should see themselves as the front end of manufacturing. Holden: If you ask designers who their custom- ers are, they say, "Well it's the lab guys who gave me the schematic and the bill of materi- als." They pay the bills, but the customer pays for manufacturing. Matties: With predictive engineering, you're talking more about a lot of simulation prior to a release into the manufacturing environment? Holden: Right, but also cognitive rules and best practices that you can use as a rule setting so you don't make that mistake of where you place IC Technology System Inputs Electrical Performance Power & Power Densities Crosstalk & Power Supply Noise Packaging Technology MCM Costs Cost Models System Interconnect Technology PCB Technology Lead Attach Technology Program analyzes: • Circuit type CMOS, ECL, etc. • Gate delay • Loading factors • Gates/chip • Chip size • Dielectric constant • Power dissipation • Wire bond • TAB • Flip chip • Substrate size • H. F. impedance model • Line dimensions • Detailed mat'l. characteristics ‰ Dielectric constant ‰ Loss tangent • Line/via spacing (design rules) • Via number and type • Number of layers • Number of signal layers • Total Manhattan length • SCP • PGA • LGA • BGA • Peripheral I/O • Multilayer ceramic • Copper polyimide • Thick film • Line dimensions • Number of chips/package • Dielectric constant • ICs • SCP & MCMs • PCBs • Backplanes (mat'l., layers, design rules) • Cables • Connectors • Flex cables • IC, packaging, PCB • Total system IC+pkg • Cost/MHz clock • Varied geometry and dielectrics • TAB, MCMs, PCBs • Chip • Package • System • Critical path delay • System clock rate • Reflections • Impedance • Inductances • Number of components (ICs, conn., discrete, trans.) • Number of electrical connections for comp. • Number of gates in critical path (pipeline) • Number of gates/system • Clock skew • Number of nets • Chip footprints • Package sizes • Average line lengths • Capacitive loads • Loaded gate delays • Interconnection delays • Static & dyn. pwr. diss. • ICs, MCMs & PCBs • Line lengths • Propagation delays • Characteristic impedances • MCM & PCB line densities • Wiring analysis • Manhattan distributions • Reflections • Power supply noises Figure 3: For predictive engineering of a PCB, there should be simulations and tradeoffs that cover all the domains that a user finds critical: costs, manufacturability, density, signal integrity and reliability.