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November 2017 • The PCB Design Magazine 35 design. Since outer layers are built up separately from the rest of the board, it becomes similarly cost effective to use different dielectric materi- als that have higher dielectric constants and are thinner than typical dielectrics. For example, when the distance between planes is reduced from 5 mils to 3 mils, a noticeable decrease in the PDN impedance occurs (Figure 5). capacitor is mounted with vias that are 80 mils (1 mm) from the capacitor pads, 40 mils (0.5 mm) from the capacitor pads, and, finally, in- side the capacitor pads themselves. The capaci- tor that is mounted using vias inside the pads clearly shows the least amount of inductance due to the mounting method. It should also be noted that one capacitor is often not sufficient to provide a PDN with an impedance below the target impedance at higher frequencies. Multiple capacitors must be used in parallel. Also, the capacitance of the power and ground planes must be relied upon to lower the PDN impedance at higher frequen- cies. This is because the planes have very little inductance. Plane Capacitance Increasing plane capacitance can be accom- plished in one of three ways. Increase the size of the planes, increase the dielectric constant of the material between the planes, or decrease the dis- tance between the planes. The latter two items are a by-product of using HDI technology in a THE IMPACT OF HDI ON PCB POWER DISTRIBUTION Figure 4: Impedance of capacitor when mounted using vias at 1 mm, 0.5 mm, and 0 mm from the pads. Figure 5: PDN impedance with plane spacing at 5 mils (upper) and 3 mils (lower).