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34 DESIGN007 MAGAZINE I JANUARY 2018 by Craig Armenti MENTOR The Challenge: Eliminate Schematic Design Errors The schematic is the controlling document for every PCB design. It captures the design intent and drives all downstream processes including simulation, analysis, layout, fabrica- tion, and assembly. As such, it is critical that the schematic accurately reflects the product's electronic requirements and specifications. Historically, the all-important task of verify- ing that the schematic is properly conveying design intent has been a manual process con- ducted by one or more hardware engineers. This verification is usually performed one sheet or one block at a time, with some automation used to assist in the process such as exporting the bill-of-materials and/or the netlist to text files or spreadsheets. Schematic verification is an accepted part of the hardware engineer's responsibility just as PCB layout verification is an accepted part of the PCB designer's responsibility. However, with today's circuit designs becoming more and more complex, time-consuming manual schematic verification is no longer an option. Manual verification of a complex circuit intro- duces significant risk by not identifying sche- matic design errors that are, in turn, passed to the downstream processes and ultimately to the fabricated board. This results in costly res- pins and increased time to market. In a recent study conducted by the Aberdeen Group, 65% of the companies surveyed cited increasing product complexity as their top PCB design challenge (Figure 1). Top Challenges in PCB Design Frequent design changes Increasing product complexity Managing design density 65% 44% 32% Figure 1: The top challenges in PCB design. (Source: Aberdeen Group)

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