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90 DESIGN007 MAGAZINE I JANUARY 2018 When supply bounce occurs, the charge that is impressed across the power delivery path results in common-mode voltage. Unfortu- nately, it is not possible to eliminate the trans- fer of charge between logic transitions but the magnitude of the radiated peaks can be lim- ited by providing a very low AC impedance path between power and ground. This is why power distribution network (PDN) planning is so important. The AC impedance of the power planes must be maintained below the target impedance up to the maximum bandwidth. The measured supply bounce is generally very small (typically 150mV) compared to the full rail voltage swing of the output signal. So, its presence does not impact on the transmit- ted signal. However, it does interfere with the reception of the signal at the load, depending on the noise margin, and can cause double clocking. This is because a TTL receiver com- pares the input voltage against the local 0V ground reference plane. CMOS devices com- pare the input voltage to the weighted aver- age of the VDD and GND while ECL compares it to VDD. Although the topology is different between logic families, the concept of supply bounce is the same. If N outputs are simultane- ously switched, then there is N times as much current and therefore the supply bounce pulse is N times larger. Figure 3 depicts the simplistic view of how supply bounce is generated. When the input to the driver transistor (right) goes high, the out- put goes low (V OL ), and a surge of current is pulled through the output ball of the BGA pack- age from the capacitive load. This current flows through inductor L GND , representing the matrix of ground balls beneath the BGA package, caus- ing a voltage glitch on the IC die substrate. There ar e typically multiple GND and VDD pads, on the BGA package, so that the parallel combina - tion reduces the overall inductance of L GND and L VDD , respectively. The victim, non-switching output (left), remains active low. However, the voltage glitch, on the substrate, is coupled into the output, and is transmitted out of the pin. Figure 3: Generation of supply bounce in a BGA package.

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