Issue link: https://iconnect007.uberflip.com/i/942744
48 DESIGN007 MAGAZINE I FEBRUARY 2018 a dense BGA package. This approach was suf- ficient as long as the active devices did not generate significant transient noise spectrum above the series resonance frequency (SRF) of the decoupling capacitors. However, higher system speeds later created the need to design the PDN systematically, to meet tighter imped- ance requirements. Designers often procrastinate about whether it is better to have a thick trace routed directly from the decoupling capacitor (decap) to the BGA power pad (Figure 1), which eliminates the power via pair and reduces the loop area. But does this reduce the inductance? This trace has to be 25 mils wide and 1 mil thick to match a via of 8 mils hole diameter with a 1 mil barrel plating thickness ( pd). The top trace has an inductance of 460pH whereas the power via pair and plane combination has a total loop inductance of 324pH. Therefore, there is 30% less inductance, in this case, by directly connecting the decap to the planes (thermals should not be used on the via plane connections). Plus, it is difficult, if not impos- sible, to route a 25mil trace to a BGA pad–par- ticularly the internal pads. 10 mil is more the norm, which would dramatically increase the trace inductance. BGA power/ground vias go directly to the plane and so should the decap power/ground vias. Also with high layer count stackups, the decaps should be placed around the perimeter of the IC on the same side of the board and routed directly to the planes. Placing decaps directly under the IC is also an obsession of the past and may increase inductance and impedes fanout and signal routing. Please see my previous column "PDN – Decoupling Capacitor Placement" for further details [1] . Target impedance is the combination of the Figure 1: Trace on the top side eliminates the two vias but increases inductance.