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FEBRUARY 2018 I DESIGN007 MAGAZINE 49 worst-case transient current and the voltage noise specification which act together to set the maximum allowable PDN impedance with assured performance. The target impedance (Ztarget) is determined based on the maximum voltage rail noise (ΔVnoise)–VDD by the rip- ple voltage–and the worst case transient cur- rent (Itransient)–maximum current by the duty cycle. Ideally, the effective impedance of the PDN should be kept below the target impedance up to the maximum required bandwidth as in Figure 2. However, if the impedance is too far below the target, then this implies that the PDN has been overdesigned which unneces- sarily increases costs with little added benefit. If your company intends building hundreds of thousands of assemblies, then the potential cost saving can be quite significant. Analyzing the PDN ensures best performance at the most cost-effective price. Target impedance is the most crucial metric when evaluating PDN performance. The fur- ther the PDN impedance is above the target impedance, the greater the risk of intermittent operation or even complete product failure. In practice, accurately calculating the tran- sient currents and the precise requirements for the target impedance can be challenging. Since we typically do not know the transient noise current excitation very accurately, it is cus- tomary instead to design the PDN to meet the required impedance profile. Also, it seems that the current portion of the target impedance equation varies from point-to-point, on the board, depending on a host of intricate rela- tionships. One must always apply engineering judgment in translating the information avail- able into the requirements for a cost-effective PDN design. Fortunately, for double data rate (DDR) memory, the power supply is only utilized for the memory ICs and the memory drivers/ receivers of the processor. Transient currents from circuits on different clock domains are statistically independent. Meaning there is no interaction between PDN current (except for any coupled noise) and therefore the DDR sup- ply is isolated from the noise of other supplies assuming good design practice. Therefore, the target impedance calculated for the DDR PDN is sufficiently accurate. However, within a single IC, there may be several circuit blocks that draw current from the same power rail. The same concept applies here: if the circuit blocks are independent Figure 2: Fundamental target impedance, VRM, capacitors and plane profiles.