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18 DESIGN007 MAGAZINE I MARCH 2018 by Andy Shaughnessy I-CONNECT007 Mentor recently released the newest version of its HyperLynx signal integrity software. This version may be the first SI tool in the indus- try to fully automate SERDES design chan- nel validation. I spoke recently with Chuck Ferry, product marketing manager with Men- tor, about the new HyperLynx and some of the new serial link design capabilities that custom- ers have been demanding. Andy Shaughnessy: Some of the newer Hyper- Lynx capabilities are focused on the users' SERDES design challenges. Part of the prob- lem with SERDES seems to be that the stan- dards for SERDES have been playing catch-up for a while, according to quite a few design engineers. What do you see going on in the SERDES standards space? Chuck Ferry: SERDES-related standards have been evolving very quickly. The number of protocols for high-speed serial data has increased drastically in the last few years. Often with each new generation of protocol, the data rates are doubling. Some of the chal- lenges hardware designers face with the recent protocols are related to differences in the types of analysis that are required and the results they must understand to properly determine if a interface will pass or fail the requirements for that given protocol. For example, the new standards rely on new metrics such as channel operating margin (COM) to determine the pass or fail criteria of the interconnect. Shaughnessy: What does it take to validate high-speed serial interface from chip-to-chip in a large system? It seems that it would be a real issue with a data center or cellular base station. Ferry: To validate a high-speed serial link end- to-end per modern protocol every aspect of the signal interconnect between the chips must be modeled accurately including the IC pack- ages, trace interconnect, as well as the charac- teristics of the drivers and receivers, including complex equalization schemes and optimiza- tion capabilities associated with those.

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