Issue link: https://iconnect007.uberflip.com/i/952929
MARCH 2018 I DESIGN007 MAGAZINE 43 However, AC coupling capacitors are com- mon sources of impedance discontinuities in high-speed serial channels. Typically, narrow trace width and close trace spacing are used to construct the 100Ω differential transmission line pair. However, as these narrow trace pairs are routed into the surface mount lands of a capacitor, the sudden widening of the copper, as they join with the capacitor lands, causes an abrupt impedance discontinuity. The effect of this discontinuity appears as excess capaci- tance because the surface mount lands, of the capacitors, act as a parallel plate with the refer- ence plane beneath. To eliminate the excess parasitic capacitance, associated with surface mount lands, a portion of the reference plane, that is directly beneath the component, should be removed. This allows the signal that traverses through the capacitor to reference a lower plane (further away) and reduces the parasitic capacitance, thereby mini - mizing the impedance mismatch. This principle should also be applied to surface mount con- nectors if present in the path (Figure 3). On the left there are two capacitors which are referenced to the plane on layer 2. Whereas, the picture on the right shows the optimized structure with the plane cut outs included. The lands then reference to the layer 3 plane increasing the impedance. The board stackup and trace geometries (Figure 4) are designed to provide a 100Ω differential signal. All traces and plane layers are 1 oz. copper. The width of the surface mount lands is set to 20mils to match the width of the 0402 type capacitors. And, the length of the cut out is equal to the end-to-end distance of the two surface mount lands. The iCD Stackup Planner can be used Figure 3: AC coupling capacitors (left) with plane cut-outs and GND vias (right).