Issue link: https://iconnect007.uberflip.com/i/981887
MAY 2018 I DESIGN007 MAGAZINE 67 the different stages of the design process, from schematic to placement to routing. Space to Experiment One of big issues that engineers have typi- cally run up against is that the experimenta- tion environment (the Post-it Note, to con- tinue our analogy) was kept separate from the design process. While the two tasks are often performed separately, it is also vital to be able to transfer the constraints developed in these virtual designs into the real-world design once they are judged appropriate. Modern EDA tools take this approach, with a constraint managing mechanism holding the constraint data of a design from schematic to manufacturing. The designer can then navi- gate through the constraints and modify them. The key issue with this approach is to get the constraints into the database without having to type in lots of numbers and data. Another important aspect to consider is that constraints Figure 3: JEDEC DDR4 topology rule and equivalent CR-8000 topology template. V TT 3 L 1 L 0 P L3 L3 L0 L2 L4 L2 via DRAM #2 via via DRAM #1 via DRAM #3 via DRAM #4 via via DRAM #5 MAIN Memory Controller PKG Length B U T S t u o k a e r B t u o k a e r B t u o k a e r B R TT = 39Ω UG583_c2_23_073015 L3