Issue link: https://iconnect007.uberflip.com/i/992528
16 PCB007 MAGAZINE I JUNE 2018 step more capable. An example is the smart- phone boards we plate at some of these big Asian shops; they have dozens of these giant vertical continuous platers, so yeah, cycle time to them is a big deal, because every new line is multi-million-dollar CapEx. It is a big deal if we can trim time off, and we do that. There's a continuous drive. I think this fits exactly in with your theme. Kologe: There's also a constant push to bump up our current densities. Whether it's strict DC or it's pulse plating for high aspect ratio, ev- erything we can do to reduce that cycle time. Just like you said, Bar- ry, there are a couple of places where we have been able to take two processes and turn it into one. We have this product we featured at IPC APEX EXPO, the VF-TH, which is via filling conformal through-hole plating of electroless copper in one step instead of do- ing the filling with a mask, stripping that, im- aging it, and then doing the conformal plating. Now it's one bath, so that's a huge value prop- osition right there. Matties: I think people will jump on that, be- cause you're also reducing the chance for fail- ure as well by eliminating steps. Cullen: That's 100% right. That's another thing that came out of the technology roadmap ses- sions. They were technology sessions, but the guys kept coming back saying, "If I have five steps and you guys are happy to advertise that your defect rate is 0.05 ppm or whatever, but you know, in my circuit board shop I've got 150 steps and you start adding all those up and if I have a couple of steps that are a little bit out of whack, I get 20% failure." There are some big, new investments for high-tech IC substrates, and they are not running profitably right now because their defect rate is 25–30%. So they don't care so much about adopting new tech- nology. They're obsessed with reducing defect rates on every single process step. Matties: That's got to be the priority. Eliminate defects and then focus on throughput speeds. Cullen: But then, at the same time, they're challenged because Apple and Samsung come in and say, "Oh, now you're going to build to this even tinier micron line/space." So in that case, they've got to adopt new processes, and new processes have high defects, right? But if they don't do it, they drop out of the supply chain. Matties: With HDI coming into the automotive space—I think the stat is by 2020, 50% of the value of the cars is going to be electronics— what challenges are you seeing? Cullen: Frankly, I think that the adoption of HDI into automotive is slow just because of fear, not because of reality. They're going to get much better circuitry when they deploy it, right? Happy Holden: Well, we've been covering up the problem, but we have a massive problem in HDI reliability on military boards, and a lot of my time at IPC APEX EXPO was spent on this. Frankly, it's a dilemma that the process- es aren't optimized. We're not sure that we are using the right design rules. We seem to have a problem with a spongy electroless. We're see- ing a lot of failure of stacked vias, things like that, with one set of vias delaminating from the plating underneath it right at the electro- less line. Cullen: Yes, Happy, I've seen some of this on circuitry blogs, and posts that have been for- warded to me, and I can speculate on this. We do continuously push HDI manufacturers to a direct metallization to remove that extra layer of copper between the foil copper and the plat- ed copper. Even the direct metallization sys- tems now are including ways to prevent the di- rect metallization of material, like the carbon Jordan Kologe