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Design007-Nov2018

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42 DESIGN007 MAGAZINE I NOVEMBER 2018 ranging from the 5V input power to the board to 0.75V DDR3 VTT reference voltage. These supplies required six layers (including ground) of the 10-layer stackup, which left only four layers for signal routing. The methodology I follow to define the planes is as follows. First, it is beneficial to define the power supply regions in conjunc- tion with placement. Group all components by functionality and their common power supply. Second, work on the critical circuits first and ensure there is a contiguous ground plane on one side and the corresponding power plane on the other. This creates a minimum loop area and a low-inductance return current path. Third, segregate critical circuits with ground planes. For example, the top portion of a sym- metrical stackup can be used for one circuit and the bottom for another. Fourth, arrange the power regions so that they do not overlap on adjacent layers because coupling between different supplies can transfer plane noise. A ground plane in between power planes prevents this and also adds valuable planar capacitance. Next, keep the regions as square as possible because a long, rectangular shape plane can create rogue waves in the plane cavities. Lastly, ensure that no signal crosses a split in the ground plane into a different domain. Power planes can be split into many differ- ent power areas (Figure 3). And since digital circuits are normally referenced to the same ground, there is no real need to split a ground plane. As mentioned in Part 2, route fences (keep-outs) can be used to control the routing and prevent signals from crossing over into dif- ferent logic domains. Split ground planes cre- ate discontinuities of impedance, crosstalk, and EMI, and should not be used. Controlled routing is the key to a successful mixed-signal design. The ground planes should not be split; instead, they should be partitioned, and a pass- through gap should be left in the route keep- out so that control signals can enter and leave the sensitive areas. V. Optimize the Power Distribution Networks (PDNs): Create a low AC impedance delivery path by optimizing the bypass and decoupling capacitors, and mount inductance and plane resonance from DC to the maximum required frequency (including harmonics). The PDN must accommodate variances of switching current with as little change in power supply voltage as possible (a 5% volt- age ripple is a typical requirement). The goal of PDN planning is to design a stable power source for all the required power supplies. Ide- ally, the effective impedance of the PDN should be kept as low as possible up to the maximum operating frequency. Figure 3: Supplies poured under an IC on multiple layers separated by ground planes. Figure 4: Typical PDN topology.

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