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72 DESIGN007 MAGAZINE I APRIL 2022 e general trend in electronics is to improve performance and minimize product size, oen leading to more complex printed circuit boards and higher component density. Semiconduc- tor packages in particular have become more complex, with many having multiple functions interconnected within the package or onto the silicon itself. For products with very high com- ponent density, companies soon realize that 100% test-probe access may not be possible. For example: • A significant number of circuit boards include components assembled onto both sides, limiting access for physical probing • It is impossible to probe the terminals of the very fine-pitch array configured com- ponents to identify functional or assembly process-related defects Design for Test, Part 3 • Very high density, small-size circuit boards do not always have accessible test lands, making it challenging to probe suspected nodes Programmable logic devices (PLDs) and flash memory devices, for example, are oen sup- plied in array packaging and soldered directly onto the circuit board. When a design includes programmable devices from multiple sources, the user must oen rely on different soware variations for programming these devices. e focus of Part 1 and Part 2 of this "Design for Test" series was on bare-board testing and fixed-probe assembly test. Information gath- ered for Part 3 furnishes the designer with an overview of preparing for boundary scan test- ing, an integrated method for testing intercon- nects on populated printed circuit boards. Designers Notebook by Vern Solberg, CONSULTANT